kernel/linux.git/include/linux/mtd, branch v6.6.132

mtd: spinand: Fix kernel doc

2026-03-04T12:20:03+00:00

[ Upstream commit a57b1f07d2d35843a7ada30c8cf9a215c0931868 ] The @data buffer is 5 bytes, not 4, it has been extended for the need of devices with an extra ID bytes. Fixes: 34a956739d29 ("mtd: spinand: Add support for 5-byte IDs") Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal Signed-off-by: Sasha Levin

mtd: spinand: Add support for 5-byte IDs

2024-04-03T13:28:58+00:00

commit 34a956739d295de6010cdaafeed698ccbba87ea4 upstream. E.g. ESMT chips will return an identification code with a length of 5 bytes. In order to prevent ambiguity, flash chips would actually need to return IDs that are up to 17 or more bytes long due to JEDEC's continuation scheme. I understand that if a manufacturer ID is located in bank N of JEDEC's database (there are currently 16 banks), N - 1 continuation codes (7Fh) need to be added to the identification code (comprising of manufacturer ID and device ID). However, most flash chip manufacturers don't seem to implement this (correctly). Signed-off-by: Ezra Buehler Reviewed-by: Martin Kurbanov Tested-by: Martin Kurbanov Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20240125200108.24374-2-ezra@easyb.ch Cc: Hauke Mehrtens Signed-off-by: Greg Kroah-Hartman

mtd: rawnand: Prevent crossing LUN boundaries during sequential reads

2024-02-01T00:18:50+00:00

commit bbcd80f53a5e8c27c2511f539fec8c373f500cf4 upstream. The ONFI specification states that devices do not need to support sequential reads across LUN boundaries. In order to prevent such event from happening and possibly failing, let's introduce the concept of "pause" in the sequential read to handle these cases. The first/last pages remain the same but any time we cross a LUN boundary we will end and restart (if relevant) the sequential read operation. Cc: stable@vger.kernel.org Fixes: 003fe4b9545b ("mtd: rawnand: Support for sequential cache reads") Signed-off-by: Miquel Raynal Tested-by: Martin Hundebøll Link: https://lore.kernel.org/linux-mtd/20231215123208.516590-2-miquel.raynal@bootlin.com Signed-off-by: Greg Kroah-Hartman

mtd: rawnand: Ensure the nand chip supports cached reads

2023-10-16T08:47:22+00:00

Both the JEDEC and ONFI specification say that read cache sequential support is an optional command. This means that we not only need to check whether the individual controller supports the command, we also need to check the parameter pages for both ONFI and JEDEC NAND flashes before enabling sequential cache reads. This fixes support for NAND flashes which don't support enabling cache reads, i.e. Samsung K9F4G08U0F or Toshiba TC58NVG0S3HTA00. Sequential cache reads are now only available for ONFI and JEDEC devices, if individual vendors implement this, it needs to be enabled per vendor. Tested on i.MX6Q with a Samsung NAND flash chip that doesn't support sequential reads. Fixes: 003fe4b9545b ("mtd: rawnand: Support for sequential cache reads") Cc: stable@vger.kernel.org Signed-off-by: Rouven Czerwinski Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230922141717.35977-1-r.czerwinski@pengutronix.de

Merge tag 'nand/for-6.6' into mtd/next

2023-08-28T14:37:38+00:00

Raw NAND core changes: * Fix -Wvoid-pointer-to-enum-cast warning * Export 'nand_exit_status_op()' * dt-bindings: Fix nand-controller.yaml license Raw NAND controller driver changes: * Omap, Omap2, Samsung, Atmel, fsl_upm, lpc32xx_slc, lpc32xx_mlc, STM32_FMC2, sh_ftlctl, MXC, Sunxi: - Use devm_platform_get_and_ioremap_resource() * Orion, vf610_nfc, Sunxi, STM32_FMC2, MTK, mpc5121, lpc32xx_slc, Intel, FSMC, Arasan: - Use helper function devm_clk_get_optional_enabled() * Brcmnand: - Use devm_platform_ioremap_resource_byname() - Propagate init error -EPROBE_DEFER up - Propagate error and simplify ternary operators - Fix mtd oobsize - Fix potential out-of-bounds access in oob write - Fix crash during the panic_write - Fix potential false time out warning - Fix ECC level field setting for v7.2 controller * fsmc: Handle clk prepare error in fsmc_nand_resume() * Marvell: Add support for AC5 SoC * Meson: - Support for 512B ECC step size - Fix build error - Use NAND core API to check status - dt-bindings: * Make ECC properties dependent * Support for 512B ECC step size * Drop unneeded quotes * Oxnas: Remove driver and bindings * Qcom: - Conversion to ->exec_op() - Removal of the legacy interface - Two full series of improvements/misc fixes * Use the BIT() macro * Use u8 instead of uint8_t * Fix alignment with open parenthesis * Fix the spacing * Fix wrong indentation * Fix a typo * Early structure initialization * Fix address parsing within ->exec_op() * Remove superfluous initialization of "ret" * Rename variables in qcom_op_cmd_mapping() * Handle unsupported opcode in qcom_op_cmd_mapping() * Fix the opcode check in qcom_check_op() * Use EOPNOTSUPP instead of ENOTSUPP * Wrap qcom_nand_exec_op() to 80 columns * Unmap sg_list and free desc within submic_descs() * Simplify the call to nand_prog_page_end_op() * Do not override the error no of submit_descs() * Sort includes alphabetically * Clear buf_count and buf_start in raw read * Add read/read_start ops in exec_op path * vf610_nfc: Do not check 0 for platform_get_irq() SPI-NAND changes: * gigadevice: Add support for GD5F1GQ{4,5}RExxH * esmt: Add support for F50D2G41KA * toshiba: Add support for T{C,H}58NYG{0,2}S3HBAI4 and TH58NYG3S0HBAI6 Signed-off-by: Miquel Raynal

mtd: rawnand: export 'nand_exit_status_op()'

2023-07-12T11:42:52+00:00

Export this function to work in pair with 'nand_status_op()' which is already exported. Signed-off-by: Arseniy Krasnov Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230705104403.696680-2-AVKrasnov@sberdevices.ru

mtd: use refcount to prevent corruption

2023-07-12T11:30:08+00:00

When underlying device is removed mtd core will crash in case user space is holding open handle. Need to use proper refcounting so device is release only when has no users. Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230620131905.648089-2-alexander.usyskin@intel.com

mtd: block: use a simple bool to track open for write

2023-06-12T14:04:04+00:00

Instead of propagating the fmode_t, just use a bool to track if a mtd block device was opened for writing. Signed-off-by: Christoph Hellwig Reviewed-by: Hannes Reinecke Acked-by: Christian Brauner Acked-by: Richard Weinberger Link: https://lore.kernel.org/r/20230608110258.189493-23-hch@lst.de Signed-off-by: Jens Axboe

Merge tag 'nand/for-6.4' into mtd/next

2023-04-19T18:39:03+00:00

Raw NAND core changes: * Convert to platform remove callback returning void * Fix spelling mistake waifunc() -> waitfunc() Raw NAND controller driver changes: * imx: Remove unused is_imx51_nfc and imx53_nfc functions * omap2: Drop obsolete dependency on COMPILE_TEST * orion: Use devm_platform_ioremap_resource() * qcom: - Use of_property_present() for testing DT property presence - Use devm_platform_get_and_ioremap_resource() * stm32_fmc2: Depends on ARCH_STM32 instead of MACH_STM32MP157 * tmio: Remove reference to config MTD_NAND_TMIO in the parsers Raw NAND manufacturer driver changes: * hynix: Fix up bit 0 of sdr_timing_mode SPI-NAND changes: * Add support for ESMT F50x1G41LB Signed-off-by: Miquel Raynal

mtd: spi-nor: Stop exporting spi_nor_restore()

2023-04-04T06:43:50+00:00

Some SPI NOR controllers that used this method were moved to drivers/spi/. We don't accept new support for the existing SPI NOR controllers drivers under drivers/mtd/spi-nor/controllers/ and we encourage their owners to move the drivers under drivers/spi/. Make spi_nor_restore() private as we're going to use it just in core.c. Link: https://lore.kernel.org/r/20230331074606.3559258-8-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus