Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v6.19.11 2025-11-12T08:35:14+00:00 2025-11-12T08:35:14+00:00 Tariq Toukan tariqt@nvidia.com 2025-11-11T12:24:48+00:00 urn:sha1:5422318e27d7a4662701f518e2e51b9f73a331b1 This patch exposes new link mode for 1600Gbps, utilizing 8 lanes at 200Gbps per lane. Co-developed-by: Yael Chemla <ychemla@nvidia.com> Reviewed-by: Shahar Shitrit <shshitrit@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1762863888-1092798-1-git-send-email-tariqt@nvidia.com Signed-off-by: Leon Romanovsky <leon@kernel.org> 2025-03-07T01:53:34+00:00 Shahar Shitrit shshitrit@nvidia.com 2025-03-04T16:06:15+00:00 urn:sha1:a2f61f1db85532e72fb8a3af51b06df94bb82912 The port header is a general file under include, yet it contains declarations for functions that are either not exported or exported but not used outside the mlx5_core driver. To enhance code organization, we move these declarations to mlx5_core.h, where they are more appropriately scoped. This refactor removes unnecessary exported symbols and prevents unexported functions from being inadvertently referenced outside of the mlx5_core driver. Signed-off-by: Shahar Shitrit <shshitrit@nvidia.com> Reviewed-by: Carolina Jubran <cjubran@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20250304160620.417580-2-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 2025-02-06T09:14:01+00:00 Jianbo Liu jianbol@nvidia.com 2025-02-03T21:35:12+00:00 urn:sha1:ee0a4fc396f1b6fd1b34e99754896961fb67e4e3 This patch exposes new link modes using 200Gbps per lane, including 200G, 400G and 800G modes. Signed-off-by: Jianbo Liu <jianbol@nvidia.com> Reviewed-by: Shahar Shitrit <shshitrit@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com> 2024-07-01T12:38:05+00:00 Mark Zhang markzhang@nvidia.com 2024-06-16T16:08:42+00:00 urn:sha1:3b43399b297c52cfe4dfe0194b6ad89d52bf8c35 Support the new "plane_ind" field when querying port PTYS registers. This is needed when querying the rate of a plane port. Signed-off-by: Mark Zhang <markzhang@nvidia.com> Link: https://lore.kernel.org/r/1f703c36306aa46917fcd88eadbb23b3e380d526.1718553901.git.leon@kernel.org Signed-off-by: Leon Romanovsky <leonro@nvidia.com> 2023-09-26T09:38:50+00:00 Patrisious Haddad phaddad@nvidia.com 2023-09-20T10:07:43+00:00 urn:sha1:b28ad32442bec2f0d9cb660d7d698a1a53c13d08 Rename 400G_8X speed to comply to naming convention. Signed-off-by: Patrisious Haddad <phaddad@nvidia.com> Reviewed-by: Mark Zhang <markzhang@nvidia.com> Link: https://lore.kernel.org/r/ac98447cac8379a43fbdb36d56e5fb2b741a97ff.1695204156.git.leon@kernel.org Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Leon Romanovsky <leon@kernel.org> 2023-09-26T09:38:46+00:00 Patrisious Haddad phaddad@nvidia.com 2023-09-20T10:07:42+00:00 urn:sha1:948f0bf5ad6ac1e5f19f6aa8e7da4a950d66b661 Add a check for 800G_8X speed when querying PTYS and report it back correctly when needed. Signed-off-by: Patrisious Haddad <phaddad@nvidia.com> Reviewed-by: Mark Zhang <markzhang@nvidia.com> Link: https://lore.kernel.org/r/26fd0b6e1fac071c3eb779657bb3d8ba47f47c4f.1695204156.git.leon@kernel.org Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Leon Romanovsky <leon@kernel.org> 2023-03-16T05:12:08+00:00 Gal Pressman gal@nvidia.com 2023-03-14T05:42:29+00:00 urn:sha1:028522e2844393abc44f7bd7477eb4a455f01579 Downstream patches require devlink params to access the PTYS register, move the needed functions from mlx5e to the core layer. Signed-off-by: Gal Pressman <gal@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Link: https://lore.kernel.org/r/20230314054234.267365-11-saeed@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org> 2022-04-06T07:15:03+00:00 Borislav Petkov bp@suse.de 2022-04-05T15:15:16+00:00 urn:sha1:0276bd3a94c072de3f69b5afe6224e488cc76635 Fix: drivers/infiniband/hw/mlx5/main.c: In function ‘translate_eth_legacy_proto_oper’: drivers/infiniband/hw/mlx5/main.c:370:2: error: case label does not reduce to an integer constant case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): ^~~~ See https://lore.kernel.org/r/YkwQ6%2BtIH8GQpuct@zn.tnic for the gory details as to why it triggers with older gccs only. Link: https://lore.kernel.org/all/20220405151517.29753-11-bp@alien8.de Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Leon Romanovsky <leon@kernel.org> Cc: Saeed Mahameed <saeedm@nvidia.com> Cc: linux-rdma@vger.kernel.org Cc: netdev@vger.kernel.org Signed-off-by: Leon Romanovsky <leonro@nvidia.com> 2022-03-11T07:38:25+00:00 Gal Pressman gal@nvidia.com 2022-01-17T13:53:06+00:00 urn:sha1:fcb610a86c53dfcfbb2aa62e704481112752f367 The assumption that the first byte in the module mapping dword is the module number shouldn't be hard-coded in the driver, but come from mlx5_ifc structs. While at it, fix the incorrect width for the 'rx_lane' and 'tx_lane' fields. Signed-off-by: Gal Pressman <gal@nvidia.com> Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> 2022-03-11T07:38:24+00:00 Gal Pressman gal@nvidia.com 2022-01-17T13:14:44+00:00 urn:sha1:271907ee2f29cd1078fd219f0778fd824fb1971c The MCIA register supports either 12 or 32 dwords, use the correct value by querying the capability from the MCAM register. Signed-off-by: Gal Pressman <gal@nvidia.com> Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>