kernel/linux.git/include/linux/mlx5/eswitch.h, branch v7.2-rc1Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v7.2-rc12026-05-07T02:03:37+00:00net/mlx5: E-Switch, serialize representor lifecycle2026-05-07T02:03:37+00:00Mark Blochmbloch@nvidia.com2026-05-03T20:27:24+00:00urn:sha1:32a72840ee300fe88e9f31dc55f9ae1dacdc8b8d
Representor callbacks can be registered and unregistered while the
E-Switch is already in switchdev mode, and the same E-Switch may also be
reconfigured by devlink, VF changes and SF changes. Serialize these paths
with the per-E-Switch representor mutex instead of relying on ad-hoc bit
state and wait queues.
Take the representor lock around the mode transition, VF/SF representor
changes and representor ops registration. Keep mode_lock and the
representor lock unnested by using the operation flag while the mode lock
is dropped. During mode changes, drop the representor lock around the
auxiliary bus rescan because driver bind/unbind may register or unregister
representor ops.
Split representor ops registration into locked public wrappers and blocked
internal helpers, clear the ops pointer on unregister, and add nested
wrappers for the shared-FDB master IB path that registers peer
representor ops while another E-Switch representor lock is already held.
On unregister, always call __unload_reps_all_vport() before marking reps
unregistered and clearing rep_ops. The per-representor state check makes
this a no-op for types that were not loaded, so unregister no longer has
to infer load state from esw->mode.
Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20260503202726.266415-6-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
mlx5: Rename the vport number enums for host PF and VF2026-04-29T20:28:30+00:00Moshe Shemeshmoshe@nvidia.com2026-04-28T05:38:48+00:00urn:sha1:5ffd937ea4050e995bd1fabc54a2534bb7bfa0d9
Rename the vport number enums MLX5_VPORT_PF to MLX5_VPORT_HOST_PF and
MLX5_VPORT_FIRST_VF to MLX5_VPORT_FIRST_HOST_VF to indicate that these
vport indices represent the host PF and its VFs. This prepares the code
for upcoming support of an additional PF type.
Signed-off-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20260428053851.220089-2-tariqt@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>
net/mlx5e: Add correct match to check IPSec syndromes for switchdev mode2025-02-25T02:14:32+00:00Jianbo Liujianbol@nvidia.com2025-02-20T21:39:53+00:00urn:sha1:85e4a808af2545fefaf18c8fe50071b06fcbdabc
In commit dddb49b63d86 ("net/mlx5e: Add IPsec and ASO syndromes check
in HW"), IPSec and ASO syndromes checks after decryption for the
specified ASO object were added. But they are correct only for eswith
in legacy mode. For switchdev mode, metadata register c1 is used to
save the mapped id (not ASO object id). So, need to change the match
accordingly for the check rules in status table.
Signed-off-by: Jianbo Liu <jianbol@nvidia.com>
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Reviewed-by: Patrisious Haddad <phaddad@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20250220213959.504304-4-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net/mlx5: E-Switch, expose eswitch manager vport2023-12-12T07:04:04+00:00Mark Blochmbloch@nvidia.com2023-12-06T14:01:37+00:00urn:sha1:eb524d0fd46249b0b9e5d52372dc65d8b32430c3
Expose the ability the query the eswitch manager vport number.
Next patch will utilize this capability to reveal the correct
register C0 value to the users.
Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Link: https://lore.kernel.org/r/614fb0e216250e2ce3340471ec141b83ec45c7f4.1701871118.git.leon@kernel.org
Signed-off-by: Leon Romanovsky <leon@kernel.org>
net/mlx5e: Handle IPsec offload for RX datapath in switchdev mode2023-08-03T01:37:29+00:00Jianbo Liujianbol@nvidia.com2023-07-31T11:28:17+00:00urn:sha1:91bafc638ed4128eaca074fe7e88a5444db14325
Reuse tun opts bits in reg c1, to pass IPsec obj id to datapath.
As this is only for RX SA and there are only 11 bits, xarray is used
to map IPsec obj id to an index, which is between 1 and 0x7ff, and
replace obj id to write to reg c1.
Signed-off-by: Jianbo Liu <jianbol@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Link: https://lore.kernel.org/r/43d60fbcc9cd672a97d7e2a2f7fe6a3d9e9a776d.1690802064.git.leon@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net/mlx5: E-switch, Remove dependency between sriov and eswitch mode2022-07-02T18:58:26+00:00Chris Micmi@nvidia.com2022-05-30T03:07:57+00:00urn:sha1:f019679ea5f2ab650c3348a79e7d9c3625f62899
Currently, there are three eswitch modes, none, legacy and switchdev.
None is the default mode. Remove redundant none mode as eswitch mode
should always be either legacy mode or switchdev mode.
With this patch, there are two behavior changes:
1. Legacy becomes the default mode. When querying eswitch mode using
devlink, a valid mode is always returned.
2. When disabling sriov, the eswitch mode will not change, only vfs
are unloaded.
Signed-off-by: Chris Mi <cmi@nvidia.com>
Reviewed-by: Maor Dickman <maord@nvidia.com>
Reviewed-by: Roi Dayan <roid@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
net/mlx5: E-Switch, Fix resetting of encap mode when entering switchdev2021-11-16T20:20:19+00:00Paul Blakeypaulb@nvidia.com2021-05-20T14:09:58+00:00urn:sha1:d7751d6476185ff754b9dad2cba0c0a6e43ecadc
E-Switch encap mode is relevant only when in switchdev mode.
The RDMA driver can query the encap configuration via
mlx5_eswitch_get_encap_mode(). Make sure it returns the currently
used mode and not the set one.
This reverts the cited commit which reset the encap mode
on entering switchdev and fixes the original issue properly.
Fixes: 9a64144d683a ("net/mlx5: E-Switch, Fix default encap mode")
Signed-off-by: Paul Blakey <paulb@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Reviewed-by: Maor Dickman <maord@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
net/mlx5: Bridge, mark reg_c1 when pushing VLAN2021-10-05T01:10:56+00:00Vlad Buslovvladbu@nvidia.com2021-09-01T16:05:02+00:00urn:sha1:5249001d69a223811ad654884c6115d55158fd51
On ingress VLAN push also assign value 0x7FE to reg_c1 tunnel id+opts
bits (tunnel id 0, which is not a valid tunnel id, and option 0x7FE which
was reserved by one of previous patches in the series). In following patch
the reg value is matched on egress miss to restore the packet to its
original state by removing the VLAN before passing it to the software data
path.
Signed-off-by: Vlad Buslov <vladbu@nvidia.com>
Reviewed-by: Paul Blakey <paulb@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
net/mlx5: E-Switch, Add event callback for representors2021-08-05T20:49:24+00:00Mark Blochmbloch@nvidia.com2021-08-03T23:19:54+00:00urn:sha1:c8e6a9e6d6bb29db08e0b69ae97f1e46ccc5691c
This callback will allow to notify representors about relevant events
when in OFFLOADS mode. In downstream patches, this will be used to notify
about PAIR/UNPAIR devcom events.
Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Reviewed-by: Mark Zhang <markzhang@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
{net, RDMA}/mlx5: Extend send to vport rules2021-08-05T20:49:24+00:00Mark Blochmbloch@nvidia.com2021-08-03T23:19:49+00:00urn:sha1:979bf468fc543444eb750c8f8817407f509bd504
In shared FDB there is only one eswitch which is active and it receives
traffic from all representors and all vports in the HCA.
While the Ethernet representor will always reside on its native PF
the IB representor will not. Extend send to vport rule creation to
support such flows. Need to account for source vport that sends the
traffic (on which the representors resides) and the target eswitch
the traffic which reach.
Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Reviewed-by: Mark Zhang <markzhang@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>