<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/include/linux/mlx5/device.h, branch linux-5.9.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.9.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.9.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2020-07-27T14:19:00+00:00</updated>
<entry>
<title>RDMA/mlx5: Set mkey relaxed ordering by UMR with ConnectX-7</title>
<updated>2020-07-27T14:19:00+00:00</updated>
<author>
<name>Meir Lichtinger</name>
<email>meirl@mellanox.com</email>
</author>
<published>2020-07-16T10:52:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=896ec9735336f5adb576d372ed7e411bce2fc74c'/>
<id>urn:sha1:896ec9735336f5adb576d372ed7e411bce2fc74c</id>
<content type='text'>
Up to ConnectX-7 UMR is not used when user passes relaxed ordering access
flag. ConnectX-7 supports setting relaxed ordering read/write mkey
attribute by UMR, indicated by new HCA capabilities.

With ConnectX-7 driver uses UMR when user set relaxed ordering access
flag, in contrast to previous silicon models. Specifically it includes
setting relvant flags of mkey context mask in UMR control segment, and
relaxed ordering write and read flags in UMR mkey context segment.

Link: https://lore.kernel.org/r/20200716105248.1423452-4-leon@kernel.org
Signed-off-by: Meir Lichtinger &lt;meirl@mellanox.com&gt;
Reviewed-by: Michael Guralnik &lt;michaelgur@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Use MLX5_SET macro instead of local structure</title>
<updated>2020-07-27T14:19:00+00:00</updated>
<author>
<name>Meir Lichtinger</name>
<email>meirl@mellanox.com</email>
</author>
<published>2020-07-16T10:52:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2224635938814fc63004e30f7c41943812bd6f1c'/>
<id>urn:sha1:2224635938814fc63004e30f7c41943812bd6f1c</id>
<content type='text'>
Use generic mlx5 structure defined in mlx5_ifc.h to represent ConnectX
device data structures instead of using structure defined specifically for
mlx5_ib module.

Link: https://lore.kernel.org/r/20200716105248.1423452-3-leon@kernel.org
Signed-off-by: Meir Lichtinger &lt;meirl@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add interface changes required for VDPA</title>
<updated>2020-07-16T05:21:29+00:00</updated>
<author>
<name>Eli Cohen</name>
<email>eli@mellanox.com</email>
</author>
<published>2020-07-15T04:28:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8a06a79b0aa811eee6d56b3cfc738c5d08b0dc74'/>
<id>urn:sha1:8a06a79b0aa811eee6d56b3cfc738c5d08b0dc74</id>
<content type='text'>
Rename mlx5_ifc_device_virtio_emulation_cap_bits to
mlx5_ifc_virtio_emulation_cap_bits to match names produced by the
tools producing these auto generated files.

In addition missing capabilities that will be required by VDPA
implementation.

Signed-off-by: Eli Cohen &lt;eli@mellanox.com&gt;
Reviewed-by: Parav Pandit &lt;parav@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: kTLS, Improve TLS params layout structures</title>
<updated>2020-06-27T20:50:46+00:00</updated>
<author>
<name>Tariq Toukan</name>
<email>tariqt@mellanox.com</email>
</author>
<published>2020-06-26T05:59:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2d1b69ed65ee033aa541518cc9f6a815296ac493'/>
<id>urn:sha1:2d1b69ed65ee033aa541518cc9f6a815296ac493</id>
<content type='text'>
Add explicit WQE segment structures for the TLS static and progress
params.
According to the HW spec, TISN is not part of the progress params context,
take it out of it.
Rename the control segment tisn field as it could hold either a TIS or
a TIR number.

Signed-off-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Introduce TLS RX offload hardware bits</title>
<updated>2020-04-28T19:45:18+00:00</updated>
<author>
<name>Tariq Toukan</name>
<email>tariqt@mellanox.com</email>
</author>
<published>2020-04-24T19:45:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ee5cdf7a5e8945372c7496e98de2b364e095b60b'/>
<id>urn:sha1:ee5cdf7a5e8945372c7496e98de2b364e095b60b</id>
<content type='text'>
Add TLS RX offload related IFC hardware fields and enumerations.

Signed-off-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Reviewed-by: Maxim Mikityanskiy &lt;maximmi@mellanox.com&gt;
Reviewed-by: Boris Pismenny &lt;borisp@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add structure and defines for pci sync for fw update event</title>
<updated>2020-04-28T19:45:18+00:00</updated>
<author>
<name>Moshe Shemesh</name>
<email>moshe@mellanox.com</email>
</author>
<published>2020-04-24T19:45:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3df0107784ceb388039b1fe510a8c7b8816de8f0'/>
<id>urn:sha1:3df0107784ceb388039b1fe510a8c7b8816de8f0</id>
<content type='text'>
Add needed structure layouts and defines for pci sync for fw update
event. The downstream patches will include event handlers for this event
type.

Signed-off-by: Moshe Shemesh &lt;moshe@mellanox.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Refactor imm_inval_pkey field in cqe struct</title>
<updated>2020-04-28T19:45:15+00:00</updated>
<author>
<name>Raed Salem</name>
<email>raeds@mellanox.com</email>
</author>
<published>2020-04-24T19:45:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=244faedfd4d8e8c8e9f3c628d29bb74196b49743'/>
<id>urn:sha1:244faedfd4d8e8c8e9f3c628d29bb74196b49743</id>
<content type='text'>
The imm_inval_pkey field can hold four different types of data,
depends on the usage, the data could be one of the below:
- Immediate field of the received message
- Invalidate rkey
- Pkey of the packet
- Flow table metadata

Current implementation doesn't reflect the intended usage of the
field at usage time.

Reflect the different types by replace this field with a union,
modify code where this field is used to reflect its intended
usage.

Signed-off-by: Raed Salem &lt;raeds@mellanox.com&gt;
Reviewed-by: Huy Nguyen &lt;huyn@mellanox.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Introduce IPsec Connect-X offload hardware bits and structures</title>
<updated>2020-04-28T19:44:45+00:00</updated>
<author>
<name>Raed Salem</name>
<email>raeds@mellanox.com</email>
</author>
<published>2020-04-24T19:45:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2b58f6d9df50f534fe465113b69de60a2ef0e74a'/>
<id>urn:sha1:2b58f6d9df50f534fe465113b69de60a2ef0e74a</id>
<content type='text'>
Add IPsec offload related IFC structs, layouts and enumerations.

Signed-off-by: Raed Salem &lt;raeds@mellanox.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add support for RDMA TX steering</title>
<updated>2020-03-27T16:24:48+00:00</updated>
<author>
<name>Michael Guralnik</name>
<email>michaelgur@mellanox.com</email>
</author>
<published>2020-03-24T06:14:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=24670b1a31661815777c2e88b94c162e47ea43fc'/>
<id>urn:sha1:24670b1a31661815777c2e88b94c162e47ea43fc</id>
<content type='text'>
Add new RDMA TX flow steering namespace. Flow steering rules in
this namespace are used to filter transmitted RDMA traffic.

Link: https://lore.kernel.org/r/20200324061425.1570190-2-leon@kernel.org
Signed-off-by: Michael Guralnik &lt;michaelgur@mellanox.com&gt;
Reviewed-by: Maor Gottlieb &lt;maorg@mellanox.com&gt;
Reviewed-by: Mark Bloch &lt;markb@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Read MCAM register groups 1 and 2</title>
<updated>2020-01-16T22:11:19+00:00</updated>
<author>
<name>Eran Ben Elisha</name>
<email>eranbe@mellanox.com</email>
</author>
<published>2019-10-07T07:31:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=932ef155117cc5caf1108bd27664dab974ba6e89'/>
<id>urn:sha1:932ef155117cc5caf1108bd27664dab974ba6e89</id>
<content type='text'>
On load, Driver caches MCAM (Management Capabilities Mask Register)
registers. in addition to the only MCAM register group (0) the driver
already reads, here we add support for reading groups 1 and 2.

Signed-off-by: Eran Ben Elisha &lt;eranbe@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
</feed>
