<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/include/linux/mlx4/qp.h, branch v2.6.32</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v2.6.32</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v2.6.32'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2009-06-05T17:36:24+00:00</updated>
<entry>
<title>IB/mlx4: Add strong ordering to local inval and fast reg work requests</title>
<updated>2009-06-05T17:36:24+00:00</updated>
<author>
<name>Jack Morgenstein</name>
<email>jackm@dev.mellanox.co.il</email>
</author>
<published>2009-06-05T17:36:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2ac6bf4ddc87c3b6b609f8fa82f6ebbffeac12f4'/>
<id>urn:sha1:2ac6bf4ddc87c3b6b609f8fa82f6ebbffeac12f4</id>
<content type='text'>
The ConnectX Programmer's Reference Manual states that the "SO" bit
must be set when posting Fast Register and Local Invalidate send work
requests.  When this bit is set, the work request will be executed
only after all previous work requests on the send queue have been
executed.  (If the bit is not set, Fast Register and Local Invalidate
WQEs may begin execution too early, which violates the defined
semantics for these operations)

This fixes the issue with NFS/RDMA reported in
&lt;http://lists.openfabrics.org/pipermail/general/2009-April/059253.html&gt;

Signed-off-by: Jack Morgenstein &lt;jackm@dev.mellanox.co.il&gt;
Cc: &lt;stable@kernel.org&gt;
Signed-off-by: Roland Dreier &lt;rolandd@cisco.com&gt;
</content>
</entry>
<entry>
<title>mlx4_core: Add VLAN tag field to WQE control segment struct</title>
<updated>2008-07-25T17:30:06+00:00</updated>
<author>
<name>Yevgeny Petrilin</name>
<email>yevgenyp@mellanox.co.il</email>
</author>
<published>2008-07-25T17:30:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=25c94d010a8ae8605dc4d5453e0c82fa97da5d12'/>
<id>urn:sha1:25c94d010a8ae8605dc4d5453e0c82fa97da5d12</id>
<content type='text'>
Add fields for VLAN tag and insert VLAN tag flag to the control
section struct.  These fields will be used for sending ethernet
packets.

Signed-off-by: Yevgeny Petrilin &lt;yevgenyp@mellanox.co.il&gt;
Signed-off-by: Roland Dreier &lt;rolandd@cisco.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx4: Add support for memory management extensions and local DMA L_Key</title>
<updated>2008-07-23T15:12:26+00:00</updated>
<author>
<name>Roland Dreier</name>
<email>rolandd@cisco.com</email>
</author>
<published>2008-07-23T15:12:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=95d04f0735b4fc837bff9aedcc3f3efb20ddc3d1'/>
<id>urn:sha1:95d04f0735b4fc837bff9aedcc3f3efb20ddc3d1</id>
<content type='text'>
Add support for the following operations to mlx4 when device firmware
supports them:

 - Send with invalidate and local invalidate send queue work requests;
 - Allocate/free fast register MRs;
 - Allocate/free fast register MR page lists;
 - Fast register MR send queue work requests;
 - Local DMA L_Key.

Signed-off-by: Roland Dreier &lt;rolandd@cisco.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx4: Rename struct mlx4_lso_seg to mlx4_wqe_lso_seg</title>
<updated>2008-07-22T21:19:39+00:00</updated>
<author>
<name>Roland Dreier</name>
<email>rolandd@cisco.com</email>
</author>
<published>2008-07-22T21:19:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=47b374752aed1c029f995473c7c463ee3ae5fbaa'/>
<id>urn:sha1:47b374752aed1c029f995473c7c463ee3ae5fbaa</id>
<content type='text'>
Make the struct name consistent with other WQE segment struct types
defined in &lt;linux/mlx4/qp.h&gt;.

Signed-off-by: Roland Dreier &lt;rolandd@cisco.com&gt;
</content>
</entry>
<entry>
<title>mlx4_core: Add helper to move QP to ready-to-send</title>
<updated>2008-04-25T21:52:32+00:00</updated>
<author>
<name>Yevgeny Petrilin</name>
<email>yevgenyp@mellanox.co.il</email>
</author>
<published>2008-04-25T21:52:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ed4d3c1061d6f367a4ef5e1656c25af3314fe2b7'/>
<id>urn:sha1:ed4d3c1061d6f367a4ef5e1656c25af3314fe2b7</id>
<content type='text'>
Avoid duplicating code in ethernet and FC modules.

Signed-off-by: Yevgeny Petrilin &lt;yevgenyp@mellanox.co.il&gt;
Signed-off-by: Roland Dreier &lt;rolandd@cisco.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx4: Add IPoIB LSO support</title>
<updated>2008-04-17T04:09:27+00:00</updated>
<author>
<name>Eli Cohen</name>
<email>eli@dev.mellanox.co.il</email>
</author>
<published>2008-04-17T04:09:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b832be1e4007f4a54954ec68bd865ff05d6babca'/>
<id>urn:sha1:b832be1e4007f4a54954ec68bd865ff05d6babca</id>
<content type='text'>
Add TSO support to the mlx4_ib driver.

Signed-off-by: Eli Cohen &lt;eli@mellanox.co.il&gt;
Signed-off-by: Roland Dreier &lt;rolandd@cisco.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx4: Add IPoIB checksum offload support</title>
<updated>2008-04-17T04:01:10+00:00</updated>
<author>
<name>Eli Cohen</name>
<email>eli@dev.mellanox.co.il</email>
</author>
<published>2008-04-17T04:01:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8ff095ec4bce7be943beff3b330562e2f0e42167'/>
<id>urn:sha1:8ff095ec4bce7be943beff3b330562e2f0e42167</id>
<content type='text'>
ConnectX devices support checksum generation and verification of TCP
and UDP packets for UD IPoIB messages.  This patch checks if the HCA
supports this and sets the IB_DEVICE_UD_IP_CSUM capability flag if it
does.  It implements support for handling the IB_SEND_IP_CSUM send
flag and setting the csum_ok field in receive work completions.

Signed-off-by: Eli Cohen &lt;eli@mellanox.co.il&gt;
Signed-off-by: Ali Ayub &lt;ali@mellanox.co.il&gt;
Signed-off-by: Roland Dreier &lt;rolandd@cisco.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx4: Use multiple WQ blocks to post smaller send WQEs</title>
<updated>2008-02-08T21:30:02+00:00</updated>
<author>
<name>Jack Morgenstein</name>
<email>jackm@dev.mellanox.co.il</email>
</author>
<published>2008-01-28T08:40:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ea54b10c7773007e173da31fe7adcc049da33331'/>
<id>urn:sha1:ea54b10c7773007e173da31fe7adcc049da33331</id>
<content type='text'>
ConnectX HCA supports shrinking WQEs, so that a single work request
can be made of multiple units of wqe_shift.  This way, WRs can differ
in size, and do not have to be a power of 2 in size, saving memory and
speeding up send WR posting.  Unfortunately, if we do this then the
wqe_index field in CQEs can't be used to look up the WR ID anymore, so
our implementation does this only if selective signaling is off.

Further, on 32-bit platforms, we can't use vmap() to make the QP
buffer virtually contigious. Thus we have to use constant-sized WRs to
make sure a WR is always fully within a single page-sized chunk.

Finally, we use WRs with the NOP opcode to avoid wrapping around the
queue buffer in the middle of posting a WR, and we set the
NoErrorCompletion bit to avoid getting completions with error for NOP
WRs.  However, NEC is only supported starting with firmware 2.2.232,
so we use constant-sized WRs for older firmware.  And, since MLX QPs
only support SEND, we use constant-sized WRs in this case.

When stamping during NOP posting, do stamping following setting of the
NOP WQE valid bit.

Signed-off-by: Michael S. Tsirkin &lt;mst@dev.mellanox.co.il&gt;
Signed-off-by: Jack Morgenstein &lt;jackm@dev.mellanox.co.il&gt;
Signed-off-by: Roland Dreier &lt;rolandd@cisco.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx4: Implement query QP</title>
<updated>2007-07-12T22:41:00+00:00</updated>
<author>
<name>Jack Morgenstein</name>
<email>jackm@dev.mellanox.co.il</email>
</author>
<published>2007-06-21T09:27:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6a775e2ba4f7635849ade628e64723ab2beef0bc'/>
<id>urn:sha1:6a775e2ba4f7635849ade628e64723ab2beef0bc</id>
<content type='text'>
Signed-off-by: Jack Morgenstein &lt;jackm@dev.mellanox.co.il&gt;
Signed-off-by: Roland Dreier &lt;rolandd@cisco.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx4: Make sure inline data segments don't cross a 64 byte boundary</title>
<updated>2007-06-18T16:23:47+00:00</updated>
<author>
<name>Roland Dreier</name>
<email>rolandd@cisco.com</email>
</author>
<published>2007-06-18T16:23:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e61ef2416b0b92828512b6cfcd0104a02b6431fe'/>
<id>urn:sha1:e61ef2416b0b92828512b6cfcd0104a02b6431fe</id>
<content type='text'>
Inline data segments in send WQEs are not allowed to cross a 64 byte
boundary.  We use inline data segments to hold the UD headers for MLX
QPs (QP0 and QP1).  A send with GRH on QP1 will have a UD header that
is too big to fit in a single inline data segment without crossing a
64 byte boundary, so split the header into two inline data segments.

Signed-off-by: Roland Dreier &lt;rolandd@cisco.com&gt;
</content>
</entry>
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