Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v5.5.10 2020-02-11T12:37:21+00:00 2020-02-11T12:37:21+00:00 Matti Vaittinen matti.vaittinen@fi.rohmeurope.com 2020-01-20T13:45:11+00:00 urn:sha1:18e5326c7bc33118b75585ed346bb4e9cefd05ef commit 6c883472e1c11cb05561b6dd0c28bb037c2bf2de upstream. When RTC is used in 24H mode (and it is by this driver) the maximum hour value is 24 in BCD. This occupies bits [5:0] - which means correct mask for HOUR register is 0x3f not 0x1f. Fix the mask Fixes: 32a4a4ebf768 ("rtc: bd70528: Initial support for ROHM bd70528 RTC") Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-12-11T12:22:54+00:00 Ran Bi ran.bi@mediatek.com 2019-12-11T09:43:54+00:00 urn:sha1:653997eeecef95c3ead4fba1b2d27e6a5854d6cd Alarm registers high byte was reserved for other functions. This add mask in alarm registers operation functions. This also fix error condition in interrupt handler. Fixes: fc2979118f3f ("rtc: mediatek: Add MT6397 RTC driver") Signed-off-by: Ran Bi <ran.bi@mediatek.com> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1576057435-3561-6-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 2019-12-05T19:43:31+00:00 Linus Torvalds torvalds@linux-foundation.org 2019-12-05T19:43:31+00:00 urn:sha1:ec939e4c94bd3ef2fd4f34c15f8aaf79bd0c5ee1 Pull ARM SoC driver updates from Olof Johansson: "Various driver updates for platforms: - A larger set of work on Tegra 2/3 around memory controller and regulator features, some fuse cleanups, etc.. - MMP platform drivers, in particular for USB PHY, and other smaller additions. - Samsung Exynos 5422 driver for DMC (dynamic memory configuration), and ASV (adaptive voltage), allowing the platform to run at more optimal operating points. - Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas - Clock/reset control driver for TI/OMAP - Meson-A1 reset controller support - Qualcomm sdm845 and sda845 SoC IDs for socinfo" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits) firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT soc: fsl: add RCPM driver dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver soc: mediatek: Refactor bus protection control soc: mediatek: Refactor sram control ... 2019-12-05T19:28:14+00:00 Linus Torvalds torvalds@linux-foundation.org 2019-12-05T19:28:14+00:00 urn:sha1:d9e48dc2a71a836f17d1febbedb31470f957edb4 Pull pwm updates from Thierry Reding: "Various changes and minor fixes across a couple of drivers" * tag 'pwm/for-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: stm32: Pass breakinput instead of its values pwm: stm32: Remove clutter from ternary operator pwm: stm32: Validate breakinput data from DT pwm: Update comment on struct pwm_ops::apply pwm: sun4i: Fix incorrect calculation of duty_cycle/period pwm: stm32: Add power management support pwm: stm32: Split breakinput apply routine to ease PM support dt-bindings: pwm-stm32: Document pinctrl sleep state pwm: sun4i: Drop redundant assignment to variable pval dt-bindings: pwm: mediatek: Remove gratuitous compatible string for MT7629 2019-12-02T00:16:31+00:00 Linus Torvalds torvalds@linux-foundation.org 2019-12-02T00:16:31+00:00 urn:sha1:37323918cac24c89facdc009b0566b25cce94ea5 Pull MFD updates from Lee Jones: "Core Frameworks: - Add support for a "resource managed strongly uncachable ioremap" call - Provide a collection of MFD helper macros - Remove mfd_clone_cell() from MFD core - Add NULL de-reference protection in MFD core - Remove superfluous function fd_platform_add_cell() from MFD core - Honour Device Tree's request to disable a device New Drivers: - Add support for MediaTek MT6323 PMIC New Device Support: - Add support for Gemini Lake to Intel LPSS PCI - Add support for Cherry Trail Crystal Cover PMIC to Intel SoC PMIC CRC - Add support for PM{I}8950 to Qualcomm SPMI PMIC - Add support for U8420 to ST-Ericsson DB8500 - Add support for Comet Lake PCH-H to Intel LPSS PCI New Functionality: - Add support for requested supply clocks; madera-core Fix-ups: - Lower interrupt priority; rk808 - Use provided helpers (macros, group functions, defines); rk808, ipaq-micro, ab8500-core, db8500-prcmu, mt6397-core, cs5535-mfd - Only allocate IRQs on request; max77620 - Use simplified API; arizona-core - Remove redundant and/or duplicated code; wm8998-tables, arizona, syscon - Device Tree binding fix-ups; madera, max77650, max77693 - Remove mfd_cell->id abuse hack; cs5535-mfd - Remove only user of mfd_clone_cell(); cs5535-mfd - Make resources static; rohm-bd70528 Bug Fixes: - Fix product ID for RK818; rk808 - Fix Power Key; rk808 - Fix booting on the BananaPi; mt6397-core - Endian fix-ups; twl.h - Fix static error checker warnings; ti_am335x_tscadc" * tag 'mfd-next-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (47 commits) Revert "mfd: syscon: Set name of regmap_config" mfd: ti_am335x_tscadc: Fix static checker warning mfd: bd70528: Staticize bit value definitions mfd: mfd-core: Honour Device Tree's request to disable a child-device dt-bindings: mfd: max77693: Fix missing curly brace mfd: intel-lpss: Add Intel Comet Lake PCH-H PCI IDs mfd: db8500-prcmu: Support U8420-sysclk firmware dt-bindings: mfd: max77650: Convert the binding document to yaml mfd: mfd-core: Move pdev->mfd_cell creation back into mfd_add_device() mfd: mfd-core: Remove usage counting for .{en,dis}able() call-backs x86: olpc-xo1-sci: Remove invocation of MFD's .enable()/.disable() call-backs x86: olpc-xo1-pm: Remove invocation of MFD's .enable()/.disable() call-backs mfd: mfd-core: Remove mfd_clone_cell() mfd: mfd-core: Protect against NULL call-back function pointer mfd: cs5535-mfd: Register clients using their own dedicated MFD cell entries mfd: cs5535-mfd: Request shared IO regions centrally mfd: cs5535-mfd: Remove mfd_cell->id hack mfd: cs5535-mfd: Use PLATFORM_DEVID_* defines and tidy error message mfd: intel_soc_pmic_crc: Add "cht_crystal_cove_pmic" cell to CHT cells mfd: madera: Add support for requesting the supply clocks ... 2019-11-11T08:45:04+00:00 Linus Walleij linus.walleij@linaro.org 2019-10-26T21:47:32+00:00 urn:sha1:22fb3ad0cc5f578398953ddcab9c8239a08caccd There is a distinct version of the Ux500 U8420 variant with "sysclk", as can be seen from the vendor code that didn't make it upstream, this firmware lacks the ULPPLL (ultra-low power phase locked loop) which in effect means that the timer clock is instead wired to the 32768 Hz always-on clock. This has some repercussions when enabling the timer clock as the code as it stands will disable the timer clock on these platforms (lacking the so-called "doze mode") and obtaining the wrong rate of the timer clock. The timer frequency is of course needed very early in the boot, and as a consequence, we need to shuffle around the early PRCMU init code: whereas in the past we did not need to look up the PRCMU firmware version in the early init, but now we need to know the version before the core system timers are registered so we restructure the platform callbacks to the PRCMU so as not to take any arguments and instead look up the resources it needs directly from the device tree when initializing. As we do not yet support any platforms using this firmware it is not a regression, but as PostmarketOS is starting to support products with this firmware we need to fix this up. The low rate of 32kHz also makes the MTU timer unsuitable as delay timer but this needs to be fixed in a separate patch. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Lee Jones <lee.jones@linaro.org> 2019-11-11T08:45:03+00:00 Lee Jones lee.jones@linaro.org 2019-10-21T09:47:37+00:00 urn:sha1:5a47c0fbd276b7f57bd38f153e8b15784b2f6f22 The MFD implementation for reference counting was complex and unnecessary. There was only one bona fide user which has now been converted to handle the process in a different way. Any future resource protection, shared enablement functions should be handed by the parent device, rather than through the MFD subsystem API. Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> 2019-11-11T08:45:03+00:00 Lee Jones lee.jones@linaro.org 2019-10-18T12:31:39+00:00 urn:sha1:ead1c83ddd7613d9e61368dc686d014e37955192 Providing a subsystem-level API helper seems over-kill just to save a few lines of C-code. Previous commits saw us convert mfd_clone_cell()'s only user over to use a more traditional style of MFD child-device registration. Now we can remove the superfluous helper from the MFD API. Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> 2019-11-11T08:45:03+00:00 Charles Keepax ckeepax@opensource.cirrus.com 2019-10-21T13:58:13+00:00 urn:sha1:1e624fce3a1ca03fcea167cc43399d0073472edc Add the ability to get the clock for each clock input pin of the chip and enable MCLK2 since that is expected to be a permanently enabled 32kHz clock. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> 2019-11-11T08:45:02+00:00 Charles Keepax ckeepax@opensource.cirrus.com 2019-10-21T13:58:11+00:00 urn:sha1:28eafe9162b6a8b7d0266889d55567ba5a7809d5 Save a few bytes by removing some registers from the driver that are not currently used and not intended to be used at any point in the future. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>