Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v6.19.11 2025-05-13T10:12:52+00:00 2025-05-13T10:12:52+00:00 Fabrice Gasnier fabrice.gasnier@foss.st.com 2025-04-29T12:51:28+00:00 urn:sha1:4f8ceb0302b36c5f78bcc8d0e7cfa2372fba134c Add support for STM32MP25 SoC. A new hardware configuration register (HWCFGR2) has been added, to gather number of capture/compare channels, autonomous mode and input capture capability. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features. This can now be read from HWCFGR registers. Add new registers to the stm32-lptimer.h: CCMR1, CCR2, HWCFGR1/2 and VERR. Update the stm32_lptimer data struct so signal the number of capture/compare channels to the child devices. Also Remove some unused bit masks (CMPOK_ARROK / CMPOKCF_ARROKCF). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250429125133.1574167-3-fabrice.gasnier@foss.st.com Signed-off-by: Lee Jones <lee@kernel.org> 2021-10-17T09:52:29+00:00 William Breathitt Gray vilhelm.gray@gmail.com 2021-08-27T03:47:45+00:00 urn:sha1:05593a3fd1037b5fee85d3c8c28112f19e7baa06 The STM32 low-power timer permits configuration of the clock polarity via the LPTIMX_CFGR register CKPOL bits. This patch provides preprocessor defines for the supported clock polarities. Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/a111c8905c467805ca530728f88189b59430f27e.1630031207.git.vilhelm.gray@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> 2020-06-18T10:19:42+00:00 Benjamin Gaignard benjamin.gaignard@st.com 2020-06-03T12:54:36+00:00 urn:sha1:e0bcc58d876c6ece9720310509a908b7637e37cf Add defines to be able to enable/clear irq and configure one shot mode. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> 2018-01-08T11:03:35+00:00 Benjamin Gaignard benjamin.gaignard@linaro.org 2017-12-05T15:24:18+00:00 urn:sha1:fa93f5b7aac54f08dea386fa4d79aa29bf54370e Add SPDX identifier Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Philippe Ombredanne <pombredanne@nexb.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> 2017-09-04T13:49:04+00:00 Fabrice Gasnier fabrice.gasnier@st.com 2017-08-28T10:04:07+00:00 urn:sha1:e8924005b4e7964313536547d4b73406330be26d STM32 Low-Power Timer hardware block can be used for: - PWM generation - IIO trigger (in sync with PWM) - IIO quadrature encoder counter PWM and IIO timer configuration are mixed in the same registers so we need a multi fonction driver to be able to share those registers. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>