<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/include/linux/host1x.h, branch v6.6.132</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.132</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.132'/>
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<updated>2023-04-04T11:59:10+00:00</updated>
<entry>
<title>gpu: host1x: Make host1x_client_unregister() return void</title>
<updated>2023-04-04T11:59:10+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2023-03-22T17:02:12+00:00</published>
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<id>urn:sha1:1d83d1a2df0bfb6bd79400746c289e2c4edc5909</id>
<content type='text'>
This function returned zero unconditionally. Make it return no value and
simplify all callers accordingly.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Acked-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: External timeout/cancellation for fences</title>
<updated>2023-01-26T14:55:38+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2023-01-19T13:09:21+00:00</published>
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<id>urn:sha1:d5179020f5ce44fd449790a9c12ef6c1a90a2ca7</id>
<content type='text'>
Currently all fences have a 30 second timeout to ensure they are
cleaned up if the fence never completes otherwise. However, this
one size fits all solution doesn't actually fit in every case,
such as syncpoint waiting where we want to be able to have timeouts
longer than 30 seconds. As such, we want to be able to give control
over fence cancellation to the caller (and maybe eventually get rid
of the internal timeout altogether).

Here we add this cancellation mechanism by essentially adding a
function for entering the timeout path by function call, and changing
the syncpoint wait function to use it.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Implement job tracking using DMA fences</title>
<updated>2023-01-26T14:55:38+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2023-01-19T13:09:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c24973ed795fec5c12d8a822a0de99a4b7bab394'/>
<id>urn:sha1:c24973ed795fec5c12d8a822a0de99a4b7bab394</id>
<content type='text'>
In anticipation of removal of the intr API, implement job tracking
using DMA fences instead. The main two things about this are
making cdma_update schedule the work since fence completion can
now be called from interrupt context, and some complication in
ensuring the callback is not running when we free the fence.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Select context device based on attached IOMMU</title>
<updated>2022-11-25T15:14:19+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2022-09-07T08:38:42+00:00</published>
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<id>urn:sha1:8935002fc37fce1ad211d98a70f2fd42083c0594</id>
<content type='text'>
On Tegra234, engines that are programmed through Host1x channels can
be attached to either the NISO0 or NISO1 SMMU. Because of that, when
selecting a context device to use with an engine, we need to select
one that is also attached to the same SMMU.

Add a parameter to host1x_memory_context_alloc to specify which device
we are allocating a context for, and use it to pick an appropriate
context device.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
[treding@nvidia.com: update !IOMMU_API stub signature]
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Program context stream ID on submission</title>
<updated>2022-07-08T14:27:52+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2022-06-27T14:19:49+00:00</published>
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<id>urn:sha1:2486254781eab6f6119fabea78f11386c54460d2</id>
<content type='text'>
Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.

Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no residual ongoing
work that might do DMA using the new stream ID.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add context device management code</title>
<updated>2022-07-08T14:27:52+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2022-06-27T14:19:48+00:00</published>
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<id>urn:sha1:8aa5bcb61612060429223d1fbb7a1c30a579fc1f</id>
<content type='text'>
Add code to register context devices from device tree, allocate them
out and manage their refcounts.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Do not use mapping cache for job submissions</title>
<updated>2022-04-06T13:12:36+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2022-03-24T10:30:25+00:00</published>
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<id>urn:sha1:3e9c4584336149146fe15cb5703fc10a2ca2d2a0</id>
<content type='text'>
Buffer mappings used in job submissions are usually small and not
rapidly reused as opposed to framebuffers (which are usually large and
rapidly reused, for example when page-flipping between double-buffered
framebuffers). Avoid going through the mapping cache for these buffers
since the cache would also lead to leaks if nobody is ever releasing
the cache's last reference. For DRM/KMS these last references are
dropped when the framebuffers are removed and therefore no longer
needed.

While at it, also add a note about the need to explicitly remove the
final reference to the mapping in the cache.

Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Fix a kernel-doc warning</title>
<updated>2022-04-06T13:08:17+00:00</updated>
<author>
<name>Randy Dunlap</name>
<email>rdunlap@infradead.org</email>
</author>
<published>2022-04-03T22:53:54+00:00</published>
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<id>urn:sha1:fe696ccb277d332dc4e625b5b20b988b04d16c04</id>
<content type='text'>
Add @cache description to eliminate a kernel-doc warning.

include/linux/host1x.h:104: warning: Function parameter or member 'cache' not described in 'host1x_client'

Fixes: 1f39b1dfa53c ("drm/tegra: Implement buffer object cache")
Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Thierry Reding &lt;treding@nvidia.com&gt;
Cc: linux-tegra@vger.kernel.org
Cc: David Airlie &lt;airlied@linux.ie&gt;
Cc: Daniel Vetter &lt;daniel@ffwll.ch&gt;
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add host1x_channel_stop()</title>
<updated>2021-12-16T13:07:07+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-11-30T23:23:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9ca790f44606109071ab1a3a37ed99e91794c37c'/>
<id>urn:sha1:9ca790f44606109071ab1a3a37ed99e91794c37c</id>
<content type='text'>
Add host1x_channel_stop() which waits till channel becomes idle and then
stops the channel hardware. This is needed for supporting suspend/resume
by host1x drivers since the hardware state is lost after power-gating,
thus the channel needs to be stopped before client enters into suspend.

Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt; # Ouya T30
Tested-by: Paul Fertser &lt;fercerpav@gmail.com&gt; # PAZ00 T20
Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt; # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar &lt;mattmerhar@protonmail.com&gt; # Ouya T30
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add NVDEC driver</title>
<updated>2021-12-16T13:07:06+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2021-09-16T14:55:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=46f226c93d35b936aeec6eb31da932dc2e86f413'/>
<id>urn:sha1:46f226c93d35b936aeec6eb31da932dc2e86f413</id>
<content type='text'>
Add support for booting and using NVDEC on Tegra210, Tegra186
and Tegra194 to the Host1x and TegraDRM drivers. Booting in
secure mode is not currently supported.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
