kernel/linux.git/include/linux/clk/ti.h, branch v4.14.78

clk: ti: convert to use proper register definition for all accesses

2017-03-08T11:06:15+00:00

Currently, TI clock driver uses an encapsulated struct that is cast into a void pointer to store all register addresses. This can be considered as rather nasty hackery, and prevents from expanding the register address field also. Instead, replace all the code to use proper struct in place for this, which contains all the previously used data. This patch is rather large as it is touching multiple files, but this can't be split up as we need to avoid any boot breakage. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren

clk: ti: drop unnecessary MEMMAP_ADDRESSING flag

2017-03-08T11:03:07+00:00

This has been superceded by the usage of ti_clk_ll_ops for now. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren

clk: ti: move omap2_init_clk_clkdm under TI clock driver

2017-03-08T10:59:30+00:00

This is not needed outside the driver, so move it inside it and remove the prototype from the public header also. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren

clk: ti: add clkdm_lookup to the exported functions

2017-03-08T10:58:41+00:00

This will be needed to move some additional clockdomain functionality under clock driver. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren

clk: ti: remove un-used definitions from public clk_hw_omap struct

2017-03-08T10:55:51+00:00

Clksel support has been deprecated a while back, so remove these from the struct also. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren

clk: ti: dpll: add support for specifying max rate for DPLLs

2016-04-16T00:26:18+00:00

DPLLs typically have a maximum rate they can support, and this varies from DPLL to DPLL. Add support of the maximum rate value to the DPLL data struct, and also add check for this in the DPLL round_rate function. Signed-off-by: Tero Kristo Reviewed-by: Nishanth Menon Cc: Tomi Valkeinen Cc: Lokesh Vutla Signed-off-by: Stephen Boyd

clk: ti: dpll: convert DPLL support code to use clk_hw instead of clk ptrs

2016-02-22T22:16:49+00:00

Convert DPLL support code to use clk_hw pointers for reference and bypass clocks. This allows us to use clk_hw_* APIs for accessing any required parameters for these clocks, avoiding some locking problems at least with DPLL enable code; this used clk_get_rate which uses mutex but isn't good under clk_enable / clk_disable. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Stephen Boyd

Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2016-01-21T01:44:16+00:00

Pull non-urgent ARM SoC fixes from Olof Johansson: "As usual, we queue up a few fixes that don't seem urgent enough to go in through -rc. - MAINTAINERS updates to add a list for brcmstb and fix a typo - A handful of fixes for OMAP 81xx, a recently resurrected platform so these can't be considered real regressions and thus got queued. - A couple of other small fixes for scoop, sa1100 and davinci" * tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: OMAP2+: Fix randconfig build warning for dm814_pllss_data ARM: sa1100/simpad: Be sure to clamp return value ARM: scoop: Be sure to clamp return value ARM: davinci: fix a problematic usage of WARN() ARM: davinci: only select WT cache if cache is enabled ARM: OMAP2+: Remove useless check for legacy booting for dm814x ARM: OMAP2+: Enable GPIO for dm814x ARM: dts: Fix dm814x pinctrl address and mask ARM: dts: Fix dm8148 control modules ranges ARM: OMAP2+: Fix timer entries for dm814x ARM: dts: Fix some mux and divider clocks to get dm814x-evm booting ARM: OMAP2+: Add DPPLS clock manager for dm814x clk: ti: Add few dm814x clock aliases ARM: dts: Fix dm814x entries for pllss and prcm MAINTAINERS: gpio-brcmstb: Remove stray '>' MAINTAINERS: brcmstb: Include Broadcom internal mailing-list

ARM: OMAP2+: Add DPPLS clock manager for dm814x

2015-12-10T00:53:46+00:00

On dm814x we have some clocks at DPLLS and some at PRCM. Let's add a new omap_prcm_init_data entry for the DPLLS so we can initalize timer clocks early. Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren

clk: ti: omap5+: dpll: implement errata i810

2015-11-30T19:34:17+00:00

Errata i810 states that DPLL controller can get stuck while transitioning to a power saving state, while its M/N ratio is being re-programmed. As a workaround, before re-programming the M/N ratio, SW has to ensure the DPLL cannot start an idle state transition. SW can disable DPLL idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request active by setting a dependent clock domain in SW_WKUP. This errata impacts OMAP5 and DRA7 chips, so enable the errata for these. Signed-off-by: Tero Kristo Signed-off-by: Stephen Boyd