kernel/linux.git/include/linux/clk-provider.h, branch v5.15.209

clk: linux/clk-provider.h: fix kernel-doc warnings and typos

2024-03-01T12:21:52+00:00

[ Upstream commit 84aefafe6b294041b7fa0757414c4a29c1bdeea2 ] Fix spelling of "Structure". Fix multiple kernel-doc warnings: clk-provider.h:269: warning: Function parameter or member 'recalc_rate' not described in 'clk_ops' clk-provider.h:468: warning: Function parameter or member 'parent_data' not described in 'clk_hw_register_fixed_rate_with_accuracy_parent_data' clk-provider.h:468: warning: Excess function parameter 'parent_name' description in 'clk_hw_register_fixed_rate_with_accuracy_parent_data' clk-provider.h:482: warning: Function parameter or member 'parent_data' not described in 'clk_hw_register_fixed_rate_parent_accuracy' clk-provider.h:482: warning: Excess function parameter 'parent_name' description in 'clk_hw_register_fixed_rate_parent_accuracy' clk-provider.h:687: warning: Function parameter or member 'flags' not described in 'clk_divider' clk-provider.h:1164: warning: Function parameter or member 'flags' not described in 'clk_fractional_divider' clk-provider.h:1164: warning: Function parameter or member 'approximation' not described in 'clk_fractional_divider' clk-provider.h:1213: warning: Function parameter or member 'flags' not described in 'clk_multiplier' Fixes: 9fba738a53dd ("clk: add duty cycle support") Fixes: b2476490ef11 ("clk: introduce the common clock framework") Fixes: 2d34f09e79c9 ("clk: fixed-rate: Add support for specifying parents via DT/pointers") Fixes: f5290d8e4f0c ("clk: asm9260: use parent index to link the reference clock") Fixes: 9d9f78ed9af0 ("clk: basic clock hardware types") Fixes: e2d0e90fae82 ("clk: new basic clk type for fractional divider") Fixes: f2e0a53271a4 ("clk: Add a basic multiplier clock") Signed-off-by: Randy Dunlap Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20230930221428.18463-1-rdunlap@infradead.org Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw

2024-01-25T22:52:44+00:00

[ Upstream commit ee0cf5e07f44a10fce8f1bfa9db226c0b5ecf880 ] Add missing comma and remove extraneous NULL argument. The macro is currently used by no one which explains why the typo slipped by. Fixes: 2d34f09e79c9 ("clk: fixed-rate: Add support for specifying parents via DT/pointers") Signed-off-by: Théo Lebrun Link: https://lore.kernel.org/r/20231218-mbly-clk-v1-1-44ce54108f06@bootlin.com Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: fixed-rate: add devm_clk_hw_register_fixed_rate

2024-01-25T22:52:44+00:00

[ Upstream commit 1d7d20658534c7d36fe6f4252f6f1a27d9631a99 ] Add devm_clk_hw_register_fixed_rate(), devres-managed helper to register fixed-rate clock. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220916061740.87167-3-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd Stable-dep-of: ee0cf5e07f44 ("clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw") Signed-off-by: Sasha Levin

clk: asm9260: use parent index to link the reference clock

2024-01-25T22:52:44+00:00

[ Upstream commit f5290d8e4f0caa81a491448a27dd70e726095d07 ] Rewrite clk-asm9260 to use parent index to use the reference clock. During this rework two helpers are added: - clk_hw_register_mux_table_parent_data() to supplement clk_hw_register_mux_table() but using parent_data instead of parent_names - clk_hw_register_fixed_rate_parent_accuracy() to be used instead of directly calling __clk_hw_register_fixed_rate(). The later function is an internal API, which is better not to be called directly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220916061740.87167-2-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd Stable-dep-of: ee0cf5e07f44 ("clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw") Signed-off-by: Sasha Levin

Merge branch 'clk-frac-divider' into clk-next

2021-09-01T22:26:45+00:00

- Add power of two flag to fractional divider clk type * clk-frac-divider: clk: fractional-divider: Document the arithmetics used behind the code clk: fractional-divider: Introduce POWER_OF_TWO_PS flag clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience clk: fractional-divider: Export approximation algorithm to the CCF users

clk: fractional-divider: Introduce POWER_OF_TWO_PS flag

2021-08-12T19:42:00+00:00

The newly introduced POWER_OF_TWO_PS flag, when set, makes the flow to skip the assumption that the caller will use an additional 2^scale prescaler to get the desired clock rate. Reported-by: Liu Ying Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210812170025.67074-3-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd

clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience

2021-08-12T19:42:00+00:00

The providers are all located in drivers/clk/ and hence no need to export the clock operations to wider audience. Hide them by moving to drivers/clk/clk-fractional-divider.h. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210812170025.67074-2-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd

clk: Align provider-specific CLK_* bit definitions

2021-08-06T00:30:51+00:00

The definition of CLK_MULTIPLIER_ROUND_CLOSEST is not aligned to the two bit definitions next to it. A deeper inspection reveals that the alignment of CLK_MULTIPLIER_ROUND_CLOSEST does match the most common alignment. Align the bit definitions for the various provider types throughout the file at 40 columns, to increase uniformity. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/5468cd9e50cda8fc59cb6baab9413c6c0de1a974.1626257689.git.geert+renesas@glider.be Signed-off-by: Stephen Boyd

clk: divider: Add re-usable determine_rate implementations

2021-06-30T18:37:02+00:00

These are useful when running on 32-bit systems to increase the upper supported frequency limit. clk_ops.round_rate returns a signed long which limits the maximum rate on 32-bit systems to 2^31 (or approx. 2.14GHz). clk_ops.determine_rate internally uses an unsigned long so the maximum rate on 32-bit systems is 2^32 or approx. 4.29GHz. To avoid code-duplication switch over divider_{ro_,}round_rate_parent to use the new divider_{ro_,}determine_rate functions. Reviewed-by: Jerome Brunet Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210627223959.188139-2-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd

clk: divider: add devm_clk_hw_register_divider

2021-04-07T18:05:44+00:00

Add devm_clk_hw_register_divider() - devres version of clk_hw_register_divider(). Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20210331105735.3690009-3-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark