kernel/linux.git/include/linux/clk-provider.h, branch v5.10.258

clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw

2024-01-25T22:37:49+00:00

[ Upstream commit ee0cf5e07f44a10fce8f1bfa9db226c0b5ecf880 ] Add missing comma and remove extraneous NULL argument. The macro is currently used by no one which explains why the typo slipped by. Fixes: 2d34f09e79c9 ("clk: fixed-rate: Add support for specifying parents via DT/pointers") Signed-off-by: Théo Lebrun Link: https://lore.kernel.org/r/20231218-mbly-clk-v1-1-44ce54108f06@bootlin.com Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: fixed-rate: add devm_clk_hw_register_fixed_rate

2024-01-25T22:37:49+00:00

[ Upstream commit 1d7d20658534c7d36fe6f4252f6f1a27d9631a99 ] Add devm_clk_hw_register_fixed_rate(), devres-managed helper to register fixed-rate clock. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220916061740.87167-3-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd Stable-dep-of: ee0cf5e07f44 ("clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw") Signed-off-by: Sasha Levin

clk: linux/clk-provider.h: fix kernel-doc warnings and typos

2023-11-20T10:06:47+00:00

[ Upstream commit 84aefafe6b294041b7fa0757414c4a29c1bdeea2 ] Fix spelling of "Structure". Fix multiple kernel-doc warnings: clk-provider.h:269: warning: Function parameter or member 'recalc_rate' not described in 'clk_ops' clk-provider.h:468: warning: Function parameter or member 'parent_data' not described in 'clk_hw_register_fixed_rate_with_accuracy_parent_data' clk-provider.h:468: warning: Excess function parameter 'parent_name' description in 'clk_hw_register_fixed_rate_with_accuracy_parent_data' clk-provider.h:482: warning: Function parameter or member 'parent_data' not described in 'clk_hw_register_fixed_rate_parent_accuracy' clk-provider.h:482: warning: Excess function parameter 'parent_name' description in 'clk_hw_register_fixed_rate_parent_accuracy' clk-provider.h:687: warning: Function parameter or member 'flags' not described in 'clk_divider' clk-provider.h:1164: warning: Function parameter or member 'flags' not described in 'clk_fractional_divider' clk-provider.h:1164: warning: Function parameter or member 'approximation' not described in 'clk_fractional_divider' clk-provider.h:1213: warning: Function parameter or member 'flags' not described in 'clk_multiplier' Fixes: 9fba738a53dd ("clk: add duty cycle support") Fixes: b2476490ef11 ("clk: introduce the common clock framework") Fixes: 2d34f09e79c9 ("clk: fixed-rate: Add support for specifying parents via DT/pointers") Fixes: f5290d8e4f0c ("clk: asm9260: use parent index to link the reference clock") Fixes: 9d9f78ed9af0 ("clk: basic clock hardware types") Fixes: e2d0e90fae82 ("clk: new basic clk type for fractional divider") Fixes: f2e0a53271a4 ("clk: Add a basic multiplier clock") Signed-off-by: Randy Dunlap Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20230930221428.18463-1-rdunlap@infradead.org Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: asm9260: use parent index to link the reference clock

2023-11-20T10:06:47+00:00

[ Upstream commit f5290d8e4f0caa81a491448a27dd70e726095d07 ] Rewrite clk-asm9260 to use parent index to use the reference clock. During this rework two helpers are added: - clk_hw_register_mux_table_parent_data() to supplement clk_hw_register_mux_table() but using parent_data instead of parent_names - clk_hw_register_fixed_rate_parent_accuracy() to be used instead of directly calling __clk_hw_register_fixed_rate(). The later function is an internal API, which is better not to be called directly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220916061740.87167-2-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd Stable-dep-of: 84aefafe6b29 ("clk: linux/clk-provider.h: fix kernel-doc warnings and typos") Signed-off-by: Sasha Levin

Merge branches 'clk-microchip', 'clk-mmp', 'clk-unused' and 'clk-at91' into clk-next

2020-08-03T22:07:18+00:00

- Add support for SAMA7G5 SoC clks - Microchip Sparx5 DPLL clk * clk-microchip: clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file * clk-mmp: clk: mmp: avoid missing prototype warning * clk-unused: clk: drop unused function __clk_get_flags * clk-at91: clk: at91: sama7g5: add clock support for sama7g5 clk: at91: clk-utmi: add utmi support for sama7g5 clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs clk: at91: add macro for pll ids mask clk: at91: clk-programmable: add mux_table option clk: at91: clk-peripheral: add support for changeable parent rate clk: at91: clk-master: add master clock support for SAMA7G5 clk: at91: clk-generated: add mux_table option clk: at91: clk-generated: pass the id of changeable parent at registration clk: at91: replace conditional operator with double logical not clk: at91: sckc: register slow_rc with accuracy option clk: at91: sam9x60: fix main rc oscillator frequency clk: at91: sam9x60-pll: use frac when setting frequency clk: at91: sam9x60-pll: check fcore against ranges clk: at91: sam9x60-pll: use logical or for range check clk: at91: clk-sam9x60-pll: fix mul mask clk: at91: clk-generated: check best_rate against ranges clk: at91: clk-generated: continue if __clk_determine_rate() returns error clk: at91: fix possible dead lock in new drivers

clk: drop unused function __clk_get_flags

2020-08-03T20:53:34+00:00

The function __clk_get_flags has not been used since the April 2019 commit a348f05361c9 ("ARM: omap2+: hwmod: drop CLK_IS_BASIC flag usage"). Other uses were removed in June 2015, eg by commit 98d8a60eccee ("clk: Convert __clk_get_flags() to clk_hw_get_flags()"), which shows how clk_hw_get_flags can easily be used instead. Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/1596272022-14173-1-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd

clk: : drop a duplicated word

2020-07-20T22:11:34+00:00

Drop the repeated word "not" in a comment. Signed-off-by: Randy Dunlap Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20200719002830.20319-1-rdunlap@infradead.org Signed-off-by: Stephen Boyd

clk: Pass correct arguments to __clk_hw_register_gate()

2020-03-26T00:38:23+00:00

I copy/pasted these macros and forgot to update the argument names and where they're passed to. Fix it so that these macros make sense. Reported-by: Maxime Ripard Fixes: 194efb6e2667 ("clk: gate: Add support for specifying parents via DT/pointers") Signed-off-by: Stephen Boyd Link: https://lkml.kernel.org/r/20200325022257.148244-1-sboyd@kernel.org Tested-by: Maxime Ripard

Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', 'clk-freescale' and 'clk-qoriq' into clk-next

2020-01-31T21:14:26+00:00

- Support for Xilinx Versal platform clks - Display clk controller on qcom sc7180 - Video clk controller on qcom sc7180 - Graphics clk controller on qcom sc7180 - CPU PLLs for qcom msm8916 - Fixes for clk controllers on qcom msm8998 SoCs - Move qcom msm8974 gfx3d clk to RPM control - Display port clk support on qcom sdm845 SoCs - Global clk controller on qcom ipq6018 - Adjust composite clk to new way of describing clk parents - Add a driver for BCLK of Freescale SAI cores * clk-imx: (32 commits) clk: imx: Add support for i.MX8MP clock driver dt-bindings: imx: Add clock binding doc for i.MX8MP clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API clk: imx: imx8mq: Switch to clk_hw based API clk: imx: imx8mm: Switch to clk_hw based API clk: imx: imx8mn: Switch to clk_hw based API clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API clk: imx: gate3: Switch to clk_hw based API clk: imx: add hw API imx_clk_hw_mux2_flags clk: imx: add imx_unregister_hw_clocks clk: imx: clk-composite-8m: Switch to clk_hw based API clk: imx: clk-pll14xx: Switch to clk_hw based API clk: imx7up: Rename the clks to hws clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based clk: imx: Rename sccg and frac pll register to suggest clk_hw clk: imx: imx7ulp composite: Rename to show is clk_hw based clk: imx: pllv2: Switch to clk_hw based API clk: imx: pllv1: Switch to clk_hw based API ... * clk-ti: clk: ti: clkctrl: Fix hidden dependency to node name clk: ti: add clkctrl data dra7 sgx clk: ti: omap5: Add missing AESS clock clk: ti: dra7: fix parent for gmac_clkctrl clk: ti: dra7: add vpe clkctrl data clk: ti: dra7: add cam clkctrl data dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock * clk-xilinx: clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag clk: zynqmp: Fix divider calculation clk: zynqmp: Add support for get max divider clk: zynqmp: Warn user if clock user are more than allowed clk: zynqmp: Extend driver for versal dt-bindings: clock: Add bindings for versal clock driver * clk-nvidia: clk: tegra20/30: Explicitly set parent clock for Video Decoder clk: tegra20/30: Don't pre-initialize displays parent clock clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe() clk: tegra: Mark fuse clock as critical * clk-qcom: (35 commits) clk: qcom: rpmh: Sort OF match table dt-bindings: fix warnings in validation of qcom,gcc.yaml dt-binding: fix compilation error of the example in qcom,gcc.yaml clk: qcom: Add ipq6018 Global Clock Controller support clk: qcom: Add DT bindings for ipq6018 gcc clock controller clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks clk: qcom: rpmh: Add IPA clock for SC7180 clk: qcom: rpmh: skip undefined clocks when registering clk: qcom: Add video clock controller driver for SC7180 dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings clk: qcom: Add graphics clock controller driver for SC7180 dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindings dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent clk: qcom: Add display clock controller driver for SC7180 dt-bindings: clock: Introduce QCOM sc7180 display clock bindings dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration clk: qcom: alpha-pll: Remove useless read from set rate ... * clk-freescale: clk: fsl-sai: new driver dt-bindings: clock: document the fsl-sai driver clk: composite: add _register_composite_pdata() variants * clk-qoriq: clk: qoriq: add ls1088a hwaccel clocks support clk: ls1028a: Add clock driver for Display output interface dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings

Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlogic' and 'clk-allwinner' into clk-next

2020-01-31T21:12:14+00:00

- Support dangerous debugfs actions on clks with dead code - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs * clk-debugfs-danger: clk: Add support for setting clk_rate via debugfs * clk-basic-hw: clk: divider: Add support for specifying parents via DT/pointers clk: gate: Add support for specifying parents via DT/pointers clk: mux: Add support for specifying parents via DT/pointers clk: asm9260: Use parent accuracy in fixed rate clk clk: fixed-rate: Document that accuracy isn't a rate clk: fixed-rate: Add clk flags for parent accuracy clk: fixed-rate: Add support for specifying parents via DT/pointers clk: fixed-rate: Document accuracy member clk: fixed-rate: Move to_clk_fixed_rate() to C file clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy() clk: fixed-rate: Convert to clk_hw based APIs clk: gpio: Use DT way of specifying parents * clk-renesas: clk: renesas: Prepare for split of R-Car H3 config symbol dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typo clk: renesas: r7s9210: Add SPIBSC clock clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks clk: renesas: Remove use of ARCH_R8A7796 clk: renesas: rcar-gen2: Change multipliers and dividers to u8 * clk-amlogic: clk: clarify that clk_set_rate() does updates from top to bottom clk: meson: meson8b: make the CCF use the glitch-free mali mux clk: meson: pll: Fix by 0 division in __pll_params_to_rate() clk: meson: g12a: fix missing uart2 in regmap table clk: meson: meson8b: use of_clk_hw_register to register the clocks clk: meson: meson8b: don't register the XTAL clock when provided via OF clk: meson: meson8b: change references to the XTAL clock to use [fw_]name clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller dt-bindings: clock: meson8b: add the clock inputs dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding * clk-allwinner: clk: sunxi: a23/a33: Export the MIPI PLL clk: sunxi: a31: Export the MIPI PLL clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock clk: sunxi-ng: r40: Export MBUS clock clk: sunxi: use of_device_get_match_data