kernel/linux.git/include/linux/amba/serial.h, branch v6.6.131

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 156

2019-05-30T18:26:35+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1334 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Reviewed-by: Richard Fontana Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.113240726@linutronix.de Signed-off-by: Greg Kroah-Hartman

tty: amba-pl011: define flag register bits for ZTE device

2016-08-31T13:24:23+00:00

For some reason we do not really understand, ZTE hardware designers choose to define PL011 Flag Register bit positions differently from standard ones as below. Bit Standard ZTE ----------------------------------- CTS 0 1 DSR 1 3 BUSY 3 8 RI 8 0 Let's define these bits into vendor data and get ZTE PL011 supported properly. Signed-off-by: Shawn Guo Acked-by: Russell King Signed-off-by: Greg Kroah-Hartman

tty: amba-pl011: add support for ZTE UART (EXPERIMENTAL)

2015-12-14T03:59:48+00:00

Add (incomplete) support for the ZTE UART to the AMBA PL011 driver. This is similar to the ARM and ST variants, except it has a different register address layout, and requires 32-bit accesses to the registers. Use the newly introduced register tables and access size support to cope with these differences. Signed-off-by: Russell King Reviewed-by: Peter Hurley Signed-off-by: Greg Kroah-Hartman

Revert "uart: pl011: Add support to ZTE ZX296702 uart"

2015-09-04T16:14:20+00:00

This reverts commit 8cd90e50d1408c65c355084b1c7f8f9085f49c6b as with this patch the serial console is broken on lots of platforms. Reported-by: Marc Zyngier Cc: Jun Nie Acked-by: Will Deacon Tested-by: Will Deacon Signed-off-by: Greg Kroah-Hartman

uart: pl011: Add support to ZTE ZX296702 uart

2015-08-05T05:07:26+00:00

Support ZTE uart with some registers differing offset. Probe as platform device for not AMBA IP ID is available on ZTE uart. Signed-off-by: Jun Nie Signed-off-by: Greg Kroah-Hartman

treewide: Fix common typo in "identify"

2013-10-14T13:31:06+00:00

Correct common misspelling of "identify" as "indentify" throughout the kernel Signed-off-by: Maxime Jayat Signed-off-by: Jiri Kosina

ARM: PL011: Add support for Rx DMA buffer polling.

2013-03-29T16:20:05+00:00

In DMA support, The received data is not pushed to tty until the DMA buffer is filled. But some megabyte rate chips such as BT expect fast response and data should be pushed immediately. In order to fix this issue, We suggest the use of the timer for polling DMA buffer. In our test, no data loss occurred at high-baudrate as compared with interrupt- driven (We tested with 3Mbps). We changes: - We add timer for polling. If we set poll_timer to 10, every 10ms, timer handler checks the residue in the dma buffer and transfer data to the tty. Also, last_residue is updated for the next polling. - poll_timeout is used to prevent the timer's system cost. If poll_timeout is set to 3000 and no data is received in 3 seconds, we inactivate poll timer and driver falls back to interrupt-driven. When data is received again in FIFO and UART irq is occurred, we switch back to DMA mode and start polling. - We use consistent DMA mappings to avoid from the frequent cache operation of the timer function for default. - pl011_dma_rx_chars is modified. the pending size is recalculated because data can be taken by polling. - the polling time is adjusted if dma rx poll is enabled but no rate is specified. Ideal polling interval to push 1 character at every interval is the reciprocal of 'baud rate / 10 line bits per character / 1000 ms per sec'. But It is very aggressive to system. Experimentally, '10000000 / baud' is suitable to receive dozens of characters. the poll rate can be specified statically by dma_rx_poll_rate of the platform data as well. Changes compared to v1: - Use of consistent DMA mappings. - Added dma_rx_poll_rate in platform data to specify the polling interval. - Added dma_rx_poll_timeout in platform data to specify the polling timeout. Changes compared to v2: - Use of consistent DMA mappings for default. - Added dma_rx_poll_enable in platform data to adjust the polling time according to the baud rate. - remove unnecessary lock from the polling function. Signed-off-by: Chanho Min Signed-off-by: Greg Kroah-Hartman

serial: pl011: delete reset callback

2012-09-10T23:33:02+00:00

Since commit 4fd0690bb0c3955983560bb2767ee82e2b197f9b "serial: pl011: implement workaround for CTS clear event issue" the PL011 UART is no longer at risk to hang up, so get rid of the callback altogether. Cc: Rajanikanth H.V Signed-off-by: Linus Walleij Acked-by: Lee Jones Signed-off-by: Greg Kroah-Hartman

ARM: 7339/1: amba/serial.h: Include types.h for resolving dependency of type bool

2012-02-23T22:07:55+00:00

serial.h uses bool, but its definition is missing, as it doesn't include types.h. Fix this by including types.h Signed-off-by: Viresh Kumar Signed-off-by: Russell King

amba pl011: workaround for uart registers lockup

2011-06-16T19:01:57+00:00

This workaround aims to break the deadlock situation which raises during continuous transfer of data for long duration over uart with hardware flow control. It is observed that CTS interrupt cannot be cleared in uart interrupt register (ICR). Hence further transfer over uart gets blocked. It is seen that during such deadlock condition ICR don't get cleared even on multiple write. This leads pass_counter to decrease and finally reach zero. This can be taken as trigger point to run this UART_BT_WA. Workaround backups the register configuration, does soft reset of UART using BIT-0 of PRCC_K_SOFTRST_SET/CLEAR registers and restores the registers. This patch also provides support for uart init and exit function calls if present. Signed-off-by: Shreshtha Kumar Sahu Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman