Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v6.19.11 2025-12-16T23:24:09+00:00 2025-12-16T23:24:09+00:00 Konrad Dybcio konrad.dybcio@oss.qualcomm.com 2025-12-02T17:36:20+00:00 urn:sha1:45e1be5ddec98db71e7481fa7a3005673200d85c Not sure how useful it's gonna be in practice, but the definition is missing (unlike the previously-unused SC8280XP_MXC-non-_AO), so add it to allow the driver to create the corresponding pmdomain. Fixes: dbfb5f94e084 ("dt-bindings: power: rpmpd: Add sc8280xp RPMh power-domains") Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20251202-topic-8280_mxc-v2-1-46cdf47a829e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2025-12-06T01:24:29+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-12-06T01:24:29+00:00 urn:sha1:0cac5ce06e524755b3dac1e0a060b05992076d93 Pull SoC devicetree updates from Arnd Bergmann: "Three new SoCs got added in existing arm64 chip families: - Renesas R-Car X5H (R8A78000) is a new generation of automotive SoCs, based on 16 Cortex-A720 (Armv9.2) cores, which makes the the currently highest-perforance embedded SoC. - TI AM62L is a new variant of the AM62 family of industrial SoCs, this one comes without a GPU. - Qualcomm MSM8937 (Snapdragon 430) is an older mobile phone chip based on Cortex-A53, and closely related to MSM8917 (Snapdragn 425), which we already support. In addition, there are a good number of newly supported machines across SoC families: - Two Aspeed AST2600 (Cortex-A7) based BMC setups for large servers - Mobile Phones and tables based on Mediatek MT6582, Nvidia Tegra124, Qualcomm MSM8937 and Qualcomm MSM8939, - Two Laptops based on Qualcomm SoCs: one using the older sdm850, the other using x1p42100. - One Router based on Rockchips RK3568 - 24 variants of the Enclustra Mercury system-on-module, all based on 32-bit Intel/Altera SocFPGA chips, plus two boards using 64-bit SocFPGA Agilex chips.. - 30 industrial/embedded boards and single-board computers, using various chips from NXP, Rockchips, Mediatek, TI, Amlogic, Qualcomm, Spacemit, and Starfive. In total there are 783 commits here, the majority of these improving hardware support and cleaning up devicetree files across the tree, with the majority of the changes going into the Qualcomm, NXP, Renesas and Rockchips platforms" * tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (782 commits) arm64: dts: mediatek: mt8195: Fix address range for JPEG decoder core 1 ARM: dts: samsung: exynos4412-midas: turn off SDIO WLAN chip during system suspend ARM: dts: samsung: exynos4210-trats: turn off SDIO WLAN chip during system suspend ARM: dts: samsung: exynos4210-i9100: turn off SDIO WLAN chip during system suspend ARM: dts: samsung: universal_c210: turn off SDIO WLAN chip during system suspend arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs arm64: dts: Add gpio_intc node for Amlogic S7D SoCs arm64: dts: Add gpio_intc node for Amlogic S7 SoCs arm64: dts: Add gpio_intc node for Amlogic S6 SoCs arm64: dts: amlogic: s7d: add ao secure node arm64: dts: amlogic: s7: add ao secure node arm64: dts: amlogic: s6: add ao secure node arm64: dts: amlogic: Fix the register name of the 'DBI' region dts: arm64: amlogic: add a5 pinctrl node arm64: dts: amlogic: s7d: add power domain controller node arm64: dts: amlogic: s7: add power domain controller node arm64: dts: amlogic: s6: add power domain controller node dts: arm64: amlogic: Add ISP related nodes for C3 arm64: dts: meson: add initial device-tree for Tanix TX9 Pro dt-bindings: arm: amlogic: add support for Tanix TX9 Pro ... 2025-10-22T12:43:57+00:00 Finley Xiao finley.xiao@rock-chips.com 2025-10-17T09:38:33+00:00 urn:sha1:295926ef36bb83d997f9c897b67fd1a0671db52e Add power domain IDs for RV1126B SoC. Add a new compatible because register fields have changed. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 2025-10-22T12:24:47+00:00 AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com 2025-09-25T14:31:12+00:00 urn:sha1:203dfbda03540f9a99341144a24877ee8b352189 Add support for the power controllers found in the MediaTek MT8196 Chromebook SoC. This chip has three power controllers, two of which located in the SCP subsystems (where one can be directly controlled and the other can be controlled only through the HW Voter IP), and one located in the Multimedia HFRP subsystem, controllable only through the HW Voter IP. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 2025-10-21T12:36:49+00:00 Jishnu Prakash jishnu.prakash@oss.qualcomm.com 2025-09-24T23:17:07+00:00 urn:sha1:0e85936a9d492acf6ff9519a5f630a7fedb62f7f Add constants for voltage levels: LOW_SVS_D2_1, LOW_SVS_D1_1 and LOW_SVS_L0. Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 2025-10-16T09:23:57+00:00 Thierry Reding treding@nvidia.com 2025-10-09T16:10:39+00:00 urn:sha1:25937d399be2ee9852103a41aaca42d91b140d79 Add the set of power domain IDs available on the Tegra264 SoC so that they can be used in device tree files. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> 2025-09-17T14:09:14+00:00 Duje Mihanović duje@dujemihanovic.xyz 2025-09-13T21:12:48+00:00 urn:sha1:5bcf9e1d0a5da750ff180e7385b0bd4041686516 Add required syscon compatible and #power-domain-cells to the APMU controller. This is required for the SoC's power domain controller as the registers are shared. Device tree bindings for said power domains are also added. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 2025-09-04T10:21:25+00:00 hongyu.chen1 hongyu.chen1@amlogic.com 2025-08-22T05:39:55+00:00 urn:sha1:9428fff44f0c5823fde733b64a344d7a6eda3873 Add devicetree binding document and related header file for Amlogic S6 S7 S7D secure power domains. Signed-off-by: hongyu.chen1 <hongyu.chen1@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250822-pm-s6-s7-s7d-v1-1-82e3f3aff327@amlogic.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 2025-08-19T09:27:50+00:00 Dmitry Baryshkov dmitry.baryshkov@oss.qualcomm.com 2025-07-18T16:13:41+00:00 urn:sha1:94838f383a050e124c044e74a954777b8f2e6c17 Some of the Qualcomm RPM PD controllers use a common set of indices for power domains. Add generic indices for Qualcomm RPM power domain controllers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20250718-rework-rpmhpd-rpmpd-v1-3-eedca108e540@oss.qualcomm.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 2025-08-19T09:27:49+00:00 Dmitry Baryshkov dmitry.baryshkov@oss.qualcomm.com 2025-07-18T16:13:40+00:00 urn:sha1:e6e1e3b6b8f9b9b78aa0dccdde431145cefb05f5 After removing RPMh PD indices, it becomes obvious that several entries don't follow the alphabetic sorting order. Move them in order to keep the file sorted. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20250718-rework-rpmhpd-rpmpd-v1-2-eedca108e540@oss.qualcomm.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>