<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/include/dt-bindings/gpio, branch v6.12.80</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-09-25T13:49:08+00:00</updated>
<entry>
<title>dt-bindings: pinctrl: Add support for Amlogic T7 SoCs</title>
<updated>2023-09-25T13:49:08+00:00</updated>
<author>
<name>Huqiang Qin</name>
<email>huqiang.qin@amlogic.com</email>
</author>
<published>2023-09-22T09:43:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2b7eb110d3c8c744cb37782d060b942d0bc2eb8e'/>
<id>urn:sha1:2b7eb110d3c8c744cb37782d060b942d0bc2eb8e</id>
<content type='text'>
Add a new compatible name for Amlogic T7 pin controller, and add
a new dt-binding header file which document the detail pin names.

Signed-off-by: Huqiang Qin &lt;huqiang.qin@amlogic.com&gt;
Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20230922094342.637251-2-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2023-08-31T02:36:19+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2023-08-31T02:36:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4a3b1007eeb26b2bb7ae4d734cc8577463325165'/>
<id>urn:sha1:4a3b1007eeb26b2bb7ae4d734cc8577463325165</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "We have some patches to DTS[I] files in arm and arm64 as well, that
  were merged here as DT headers were being changed.

  The most interesting stuff is the Intel Tangier chip support and
  AMLogic C3 in my opinion.

  No core changes this time.

  Drivers:

   - Intel Tangier SoC pin control support

   - AMLogic C3 SoC pin control support

   - Texas Instruments AM654 SoC pin control support

   - Qualcomm SM8350 and SM6115 LPASS (Low Power Audio Sub-System) pin
     control support

   - Qualcomm PMX75 and PM7550BA (Power Management) pin control support

   - Qualcomm PMC8180 and PMC8180C (Power Management) pin control
     support

   - DROP the Oxnas driver as there is not enough of community interest
     to keep carrying this ARM(11) port

  Enhancements:

   - Bias control in the MT7986 pin control driver

   - Misc device tree binding enhancements such as the Broadcom 11351
     being converted to YAML

   - New macro: DEFINE_NOIRQ_DEV_PM_OPS() put to use

   - Clean up some SPDX headers

   - Handle non-unique devicetree subnode names in two Renesas drivers"

* tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
  pinctrl: mlxbf3: Remove gpio_disable_free()
  pinctrl: use capital "OR" for multiple licenses in SPDX
  dt-bindings: pinctrl: renesas,rza2: Use 'additionalProperties' for child nodes
  pinctrl: cherryview: fix address_space_handler() argument
  pinctrl: intel: consolidate ACPI dependency
  pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: mvebu: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: at91: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pm: Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: mediatek: assign functions to configure pin bias on MT7986
  pinctrl: mediatek: fix pull_type data for MT7981
  dt-bindings: pinctrl: aspeed: Allow only defined pin mux node properties
  dt-bindings: pinctrl: Drop 'phandle' properties
  pinctrl: lynxpoint: Make use of pm_ptr()
  pinctrl: baytrail: Make use of pm_ptr()
  pinctrl: intel: Switch to use exported namespace
  pinctrl: lynxpoint: reuse common functions from pinctrl-intel
  pinctrl: cherryview: reuse common functions from pinctrl-intel
  ...
</content>
</entry>
<entry>
<title>dt-bindings: use capital "OR" for multiple licenses in SPDX</title>
<updated>2023-08-23T20:00:31+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2023-08-23T08:45:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=440b075bd2b52c481aa240a0afeac700b436850d'/>
<id>urn:sha1:440b075bd2b52c481aa240a0afeac700b436850d</id>
<content type='text'>
Documentation/process/license-rules.rst and checkpatch expect the SPDX
identifier syntax for multiple licenses to use capital "OR".  Correct it
to keep consistent format and avoid copy-paste issues.

Correct also the format // -&gt; .* in few Allwinner binding headers as
pointed out by checkpatch:

  WARNING: Improper SPDX comment style for 'include/dt-bindings/reset/sun50i-h6-ccu.h', please use '/*' instead

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Acked-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Acked-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Link: https://lore.kernel.org/r/20230823084540.112602-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: Add compatibles for Amlogic C3 SoCs</title>
<updated>2023-07-23T19:23:16+00:00</updated>
<author>
<name>Huqiang Qin</name>
<email>huqiang.qin@amlogic.com</email>
</author>
<published>2023-07-14T12:24:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e55ef16b840f03749b290549ec3ffc4c07f550be'/>
<id>urn:sha1:e55ef16b840f03749b290549ec3ffc4c07f550be</id>
<content type='text'>
Add a new compatible name for Amlogic C3 pin controller, and add
a new dt-binding header file which document the detail pin names.

Signed-off-by: Huqiang Qin &lt;huqiang.qin@amlogic.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20230714122441.3098337-2-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: gpio: Remove FSI domain ports on Tegra234</title>
<updated>2023-06-06T12:38:58+00:00</updated>
<author>
<name>Prathamesh Shete</name>
<email>pshete@nvidia.com</email>
</author>
<published>2023-05-30T10:51:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=12382ad05110b569d95d29c637e16bbeb115acca'/>
<id>urn:sha1:12382ad05110b569d95d29c637e16bbeb115acca</id>
<content type='text'>
Ports S, T, U and V are in a separate controller that is part of the FSI
domain. Remove their definitions from the MAIN controller definitions to
get rid of the confusion.

This technically breaks ABI compatibility with old device trees. However
it doesn't cause issues in practice. The GPIO pins impacted by this are
used for non-critical functionality.

Fixes: a8b10f3d12cfc ("dt-bindings: gpio: Add Tegra234 support")
Signed-off-by: Prathamesh Shete &lt;pshete@nvidia.com&gt;
[treding@nvidia.com: rewrite commit message]
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-binding: gpio: publish binding IDs under dual license</title>
<updated>2023-01-17T20:43:55+00:00</updated>
<author>
<name>Etienne Carriere</name>
<email>etienne.carriere@linaro.org</email>
</author>
<published>2022-09-05T14:55:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=323b8d0ddb92b189ed7561e8095a9aa43968d519'/>
<id>urn:sha1:323b8d0ddb92b189ed7561e8095a9aa43968d519</id>
<content type='text'>
Changes gpio.h DT binding header file to be published under GPLv2 or
BSD-2-Clause license terms. This change allows this GPIO generic
bindings header file to be used in software components as bootloaders
and OSes that are not published under GPLv2 terms.

All contributors to gpio.h file in copy.

Cc: Stephen Warren &lt;swarren@nvidia.com&gt;
Cc: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Cc: Laxman Dewangan &lt;ldewangan@nvidia.com&gt;
Cc: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Cc: Nuno Sá &lt;nuno.sa@analog.com&gt;
Signed-off-by: Etienne Carriere &lt;etienne.carriere@linaro.org&gt;
Acked-by: Nuno Sá &lt;nuno.sa@analog.com&gt;
Acked-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20220905145555.674800-1-etienne.carriere@linaro.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: gpio: add pull-disable flag</title>
<updated>2022-07-19T08:24:17+00:00</updated>
<author>
<name>Nuno Sá</name>
<email>nuno.sa@analog.com</email>
</author>
<published>2022-07-13T13:14:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d042656a2170ce1b0d1a72d81a99bc93f0170358'/>
<id>urn:sha1:d042656a2170ce1b0d1a72d81a99bc93f0170358</id>
<content type='text'>
This extends the flags that can be used in GPIO specifiers to indicate
that no bias is intended in the pin.

Signed-off-by: Nuno Sá &lt;nuno.sa@analog.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Bartosz Golaszewski &lt;brgl@bgdev.pl&gt;
</content>
</entry>
<entry>
<title>dt-bindings: gpio: Add a header file for Amlogic Meson S4</title>
<updated>2022-01-30T01:52:45+00:00</updated>
<author>
<name>Qianggui Song</name>
<email>qianggui.song@amlogic.com</email>
</author>
<published>2022-01-13T03:10:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1713a8de4a3bf7d7d2d5759c895e486885fd1cc3'/>
<id>urn:sha1:1713a8de4a3bf7d7d2d5759c895e486885fd1cc3</id>
<content type='text'>
Add a new dt-binding header file which documents the detail pin names.

Reviewed-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Qianggui Song &lt;qianggui.song@amlogic.com&gt;
Link: https://lore.kernel.org/r/20220113031044.2665-3-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: gpio: Add Tegra241 support</title>
<updated>2021-12-23T16:12:11+00:00</updated>
<author>
<name>Akhil R</name>
<email>akhilrajeev@nvidia.com</email>
</author>
<published>2021-12-16T14:10:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9f01881beae9e40c87f3edfb81e87e973f85d272'/>
<id>urn:sha1:9f01881beae9e40c87f3edfb81e87e973f85d272</id>
<content type='text'>
Add the port definitions for the main and AON GPIO controllers found on
Tegra241 (Grace).

Signed-off-by: Akhil R &lt;akhilrajeev@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Bartosz Golaszewski &lt;brgl@bgdev.pl&gt;
</content>
</entry>
<entry>
<title>dt-bindings: gpio: msc313: Add offsets for ssd20xd</title>
<updated>2021-12-20T14:48:43+00:00</updated>
<author>
<name>Daniel Palmer</name>
<email>daniel@0x0f.com</email>
</author>
<published>2021-12-13T09:40:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e82513696eadcf71048be174b4b71f9903ba4afd'/>
<id>urn:sha1:e82513696eadcf71048be174b4b71f9903ba4afd</id>
<content type='text'>
Add the gpio offsets for the SSD201 and SSD202D chips.

Signed-off-by: Daniel Palmer &lt;daniel@0x0f.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Bartosz Golaszewski &lt;brgl@bgdev.pl&gt;
</content>
</entry>
</feed>
