kernel/linux.git/include/dt-bindings/gpio, branch v6.1.168

dt-bindings: gpio: add pull-disable flag

2022-07-19T08:24:17+00:00

This extends the flags that can be used in GPIO specifiers to indicate that no bias is intended in the pin. Signed-off-by: Nuno Sá Reviewed-by: Linus Walleij Acked-by: Rob Herring Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: Add a header file for Amlogic Meson S4

2022-01-30T01:52:45+00:00

Add a new dt-binding header file which documents the detail pin names. Reviewed-by: Martin Blumenstingl Acked-by: Rob Herring Signed-off-by: Qianggui Song Link: https://lore.kernel.org/r/20220113031044.2665-3-qianggui.song@amlogic.com Signed-off-by: Linus Walleij

dt-bindings: gpio: Add Tegra241 support

2021-12-23T16:12:11+00:00

Add the port definitions for the main and AON GPIO controllers found on Tegra241 (Grace). Signed-off-by: Akhil R Signed-off-by: Thierry Reding Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: msc313: Add offsets for ssd20xd

2021-12-20T14:48:43+00:00

Add the gpio offsets for the SSD201 and SSD202D chips. Signed-off-by: Daniel Palmer Acked-by: Rob Herring Reviewed-by: Linus Walleij Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: Add Tegra234 support

2021-12-17T11:26:13+00:00

Extend the existing Tegra186 GPIO controller device tree bindings with support for the GPIO controller found on Tegra234. The number of pins is slightly different, but the programming model remains the same. Signed-off-by: Prathamesh Shete Reviewed-by: Linus Walleij Reviewed-by: Rob Herring [treding@nvidia.com: update device tree bindings] Signed-off-by: Thierry Reding Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: Add a binding header for the MSC313 GPIO driver

2020-12-05T21:40:28+00:00

Header adds defines for the gpio number of each pad from the driver view. The gpio block seems to have enough registers for 128 lines but what line is mapped to a physical pin depends on the chip. The gpio block also seems to contain some registers that are not related to gpio but needed somewhere to go. Because of the above the driver itself uses the index of a pin's offset in an array of the possible offsets for a chip as the gpio number. Signed-off-by: Daniel Palmer Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201129110803.2461700-2-daniel@0x0f.com Signed-off-by: Linus Walleij

dt-bindings: gpio: Use Tegra186-specific include guard

2020-12-05T21:34:12+00:00

Use a unique include guard for the Tegra186 GPIO DT bindings header to avoid clashes with the DT bindings header for earlier chips. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20201127140852.123192-2-thierry.reding@gmail.com Signed-off-by: Linus Walleij

pinctrl: add compatible for Amlogic Meson A1 pin controller

2019-11-04T15:31:34+00:00

Add new compatible name for Amlogic's Meson-A1 pin controller add a dt-binding header file which document the detail pin names. Note that A1 doesn't need DS bank reg any more, use gpio reg as base. Reviewed-by: Rob Herring Reviewed-by: Neil Armstrong Signed-off-by: Qianggui Song Link: https://lore.kernel.org/r/1572004167-24150-2-git-send-email-qianggui.song@amlogic.com Signed-off-by: Linus Walleij

Merge tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

2019-06-25T11:48:32+00:00

arm64: tegra: Device tree changes for v5.3-rc1 This contains the bulk of the Tegra changes this cycle. It has a bunch of improvements across almost all boards. These are mostly small and not too exciting additions. Most notably perhaps is the continuation of Jetson Nano support, which is now mostly on feature parity with Jetson TX1. * tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (28 commits) arm64: tegra: Enable PCIe slots in P2972-0000 board arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT arm64: tegra: Add PEX DPD states as pinctrl properties arm64: tegra: Enable ACONNECT, ADMA and AGIC arm64: tegra: Add ACONNECT, ADMA and AGIC nodes arm64: tegra: Sort device tree nodes alphabetically arm64: tegra: Fix Jetson Nano GPU regulator arm64: tegra: Update Jetson TX1 GPU regulator timings arm64: tegra: Fix AGIC register range arm64: tegra: Add INA3221 channel info for Jetson TX2 arm64: tegra: Enable PWM on Jetson Nano arm64: tegra: Enable CPU sleep on Jetson Nano arm64: tegra: Add ID EEPROMs on Jetson Nano arm64: tegra: Add ID EEPROM for Jetson TX2 Developer Kit arm64: tegra: Add ID EEPROM for Jetson TX2 module arm64: tegra: Add ID EEPROM for Jetson TX1 Developer Kit arm64: tegra: Add ID EEPROM for Jetson TX1 module arm64: tegra: Don't use architected timer for suspend on Tegra210 arm64: tegra: Mark architected timer as always on arm64: tegra: Add pin control states for I2C on Tegra186 ... Signed-off-by: Olof Johansson

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 446

2019-06-05T15:37:18+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 30 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190115.962665879@linutronix.de Signed-off-by: Greg Kroah-Hartman