kernel/linux.git/include/dt-bindings/clock, branch v7.2-rc1

Merge branches 'clk-microchip' and 'clk-qcom' into clk-next

2026-06-25T14:55:47+00:00

* clk-microchip: clk: at91: keep securam node alive while mapping it clk: at91: sama7d65: add peripheral clock for I3C clk: microchip: mpfs-ccc: fix peripheral driver registration failures after oob fix clk: at91: sam9x7: Fix gmac_gclk clock definition clk: at91: sam9x7: Rename macb0_clk to gmac_clk clk: at91: sam9x7: Remove gmac peripheral clock with ID 67 clk: microchip: rename clk-core to clk-pic32 * clk-qcom: (32 commits) clk: qcom: regmap-phy-mux: Rework the implementation clk: qcom: a53: Corrected frequency multiplier for 1152MHz clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC clk: qcom: gdsc: Support enabling interconnect path for power domain dt-bindings: clock: qcom,milos-camcc: Document interconnect path interconnect: Add devm_of_icc_get_by_index() as exported API for users clk: qcom: camcc-x1p42100: Add support for camera clock controller clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks clk: qcom: videocc-x1p42100: Add support for video clock controller dt-bindings: clock: qcom: Add X1P42100 camera clock controller dt-bindings: clock: qcom: Add X1P42100 video clock controller clk: qcom: nord: negcc: add support for the USB2 PHY reset dt-bindings: clock: qcom: add the definition for the USB2 PHY reset clk: qcom: clk-rpmh: Make all VRMs optional clk: qcom: Add support for global clock controller on Hawi clk: qcom: clk-alpha-pll: Add support for Taycan EHA_T PLL clk: qcom: Add Hawi TCSR clock controller driver clk: qcom: rpmh: Add support for Hawi RPMH clocks dt-bindings: clock: qcom: Add Hawi global clock controller dt-bindings: clock: qcom: Add Hawi TCSR clock controller ...

Merge branches 'clk-ti', 'clk-samsung', 'clk-rockchip' and 'clk-spacemit' into clk-next

2026-06-25T14:55:38+00:00

* clk-ti: clk: keystone: sci-clk: fix application of sizeof to pointer clk: keystone: don't cache clock rate * clk-samsung: clk: samsung: exynos990: Fix PERIC0/1 USI clock types clk: samsung: exynos850: mark APM I3C clocks as critical * clk-rockchip: clk: rockchip: allow COMPILE_TEST builds clk: rockchip: rk3588: add GATE_GRF clocks for I2S MCLK output to IO soc: rockchip: rk3588: add SYS_GRF SOC_CON6 register offset clk: rockchip: add helper to register auxiliary GRFs clk: rockchip: allow grf_type_sys lookup in aux_grf_table dt-bindings: clock: rockchip,rk3588-cru: add I2S MCLK output to IO clock IDs * clk-spacemit: clk: spacemit: k3: Add PCIe DBI clock dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs clk: spacemit: k3: Fix PCIe clock register offset clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock

Merge branches 'clk-renesas', 'clk-socfpga', 'clk-amlogic' and 'clk-canaan' into clk-next

2026-06-25T14:55:26+00:00

* clk-renesas: (36 commits) clk: renesas: r9a08g045: Drop unused pm_domain header file clk: renesas: r8a779g0: Add DSC clock clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowing clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macro clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro clk: renesas: rzg2l: Simplify SAM PLL configuration macro clk: renesas: r8a73a4: Add ZT/ZTR trace clocks dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6 clk: renesas: r9a08g046: Add RSPI clocks and resets clk: renesas: r9a08g046: Add SSIF-2 clocks and resets clk: renesas: r9a08g046: Add RSCI clocks and resets clk: renesas: cpg-mssr: Add number of clock cells check clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable() clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS() clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocks clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets clk: renesas: r9a09g047: Add support for DSI clocks and resets clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks ... * clk-socfpga: clk: socfpga: agilex: implement l3_main_free_clk * clk-amlogic: dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock dt-bindings: clock: amlogic: Fix redundant hyphen in "amlogic,t7-gp1--pll" string. * clk-canaan: clk: canaan: Add clock driver for Canaan K230 dt-bindings: clock: Add Canaan K230 clock controller

dt-bindings: clock: qcom: Add X1P42100 camera clock controller

2026-06-07T00:50:15+00:00

Add X1P42100 camera clock controller support and clock bindings for camera QDSS debug clocks which are applicable for both X1E80100 and X1P42100 platforms. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-2-fc3af4130282@oss.qualcomm.com Signed-off-by: Bjorn Andersson

dt-bindings: clock: qcom: Add X1P42100 video clock controller

2026-06-07T00:50:15+00:00

Add device tree bindings for the video clock controller on Qualcomm X1P42100 (Purwa) SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-1-fc3af4130282@oss.qualcomm.com Signed-off-by: Bjorn Andersson

dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs

2026-06-02T07:16:59+00:00

Add clock IDs of PCIe DBI (Data Bus Interface) clock. Acked-by: Conor Dooley Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-3-c9a5e563bab3@kernel.org Signed-off-by: Yixun Lan

dt-bindings: clock: qcom: add the definition for the USB2 PHY reset

2026-05-22T02:54:09+00:00

Provide the USB2 PHY reset definition in dt-bindings for the Nord negcc module in order to enable adding the USB nodes in DTS. Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260518-nord-clk-usb2-phy-v2-1-17a86cb307c3@oss.qualcomm.com Signed-off-by: Bjorn Andersson

dt-bindings: clock: Add Canaan K230 clock controller

2026-05-21T09:55:12+00:00

This patch adds the Device Tree binding for the clock controller on Canaan k230. The binding defines the clocks and the required properties to configure them correctly. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xukai Wang Signed-off-by: Conor Dooley

dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6

2026-05-15T09:26:26+00:00

Document the ZT trace bus and ZTR trace clocks on R-Mobile APE6. These clocks supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clocks, coresight tracing can not be operated. While this does change the ABI, it does so by extending the existing clock-output-names, therefore if old software is used with new DT, the coresight tracing parts will likely fail to probe, otherwise if new software is used with an old DT, there is no impact. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260502185557.93061-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven

dt-bindings: clock: qcom: Add Hawi global clock controller

2026-05-13T16:52:46+00:00

Add device tree bindings for the global clock controller on the Qualcomm Hawi SoC. Acked-by: Rob Herring (Arm) Reviewed-by: Mike Tipton Signed-off-by: Vivek Aknurwar Link: https://lore.kernel.org/r/20260506-clk-hawi-v3-3-530b538679f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson