<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/include/acpi/actbl2.h, branch v6.6.131</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.131</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.131'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-07-10T16:49:16+00:00</updated>
<entry>
<title>ACPICA: RHCT: Add flags, CMO and MMU nodes</title>
<updated>2023-07-10T16:49:16+00:00</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2023-04-15T14:47:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=fe85f8ff2fc99897c62e3d327f853742231647fb'/>
<id>urn:sha1:fe85f8ff2fc99897c62e3d327f853742231647fb</id>
<content type='text'>
ACPICA commit 2eded5a6a13d892b7dc3be6096e7b1e8d4407600

Update RHCT table with below details.

 1) Add additional structure to describe the Cache Management
    Operation (CMO) related information.

 2) Add structure to describe MMU type.

 3) Convert the current reserved field to flags and define
    a flag to indicate timer capability.

This codefirst ECR is approved by UEFI forum and will
be part of next ACPI spec version.

Link: https://github.com/acpica/acpica/commit/2eded5a6
Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: MADT: Add RISC-V external interrupt controllers</title>
<updated>2023-07-10T16:49:16+00:00</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2023-04-15T13:49:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f3b19adef6c63c2b0778fe5918f786248a9ff897'/>
<id>urn:sha1:f3b19adef6c63c2b0778fe5918f786248a9ff897</id>
<content type='text'>
ACPICA commit 8c048cee4ea7b9ded8db3e1b3b9c14e21e084a2c

This adds 3 different external interrupt controller
definitions in MADT for RISC-V.

 1) RISC-V PLIC is a platform interrupt controller for
    handling wired interrupt in a RISC-V systems.

 2) RISC-V IMSIC is MSI interrupt controller to
    support MSI interrupts.

 3) RISC-V APLIC has dual functionality. First it can
    act like PLIC and direct all wired interrupts to
    the CPU which doesn't have MSI controller. Second,
    when the CPU has MSI controller (IMSIC), it will
    act as a converter from wired interrupts to MSI.

Update the existing RINTC structure also to support
these external interrupt controllers.

This codefirst ECR is approved by UEFI forum and will
be part of next ACPI spec version.

Link: https://github.com/acpica/acpica/commit/8c048cee
Signed-off-by: Haibo, Xu &lt;haibo1.xu@intel.com&gt;
Co-developed-by: Haibo, Xu &lt;haibo1.xu@intel.com&gt;
Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: acpi_madt_oem_data: Fix flexible array member definition</title>
<updated>2023-04-06T18:29:12+00:00</updated>
<author>
<name>Kees Cook</name>
<email>kees@outflux.net</email>
</author>
<published>2023-04-05T13:56:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2a85fc5626797f9057311a419b1d5d847d86c527'/>
<id>urn:sha1:2a85fc5626797f9057311a419b1d5d847d86c527</id>
<content type='text'>
ACPICA commit e7f6d8c1b7f79eb4b9b07f1bc09c549a2acbd6e8

Use ACPI_FLEX_ARRAY() helper to define flexible array member alone in a
struct. Fixes issue #812.

No binary changes appear in the .text nor .data sections.

Link: https://github.com/acpica/acpica/commit/e7f6d8c1
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: struct acpi_nfit_interleave: Replace 1-element array with flexible array</title>
<updated>2023-04-06T18:29:12+00:00</updated>
<author>
<name>Kees Cook</name>
<email>kees@outflux.net</email>
</author>
<published>2023-04-05T13:51:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2a5ab99847bd41ad5f0461f519d0825f163874a6'/>
<id>urn:sha1:2a5ab99847bd41ad5f0461f519d0825f163874a6</id>
<content type='text'>
ACPICA commit e66decc6fca36b59194b0947d87d6a9bec078bc3

Similar to "Replace one-element array with flexible-array", replace the
1-element array with a proper flexible array member as defined by C99.

This allows the code to operate without tripping compile-time and run-
time bounds checkers (e.g. via __builtin_object_size(), -fsanitize=bounds,
and/or -fstrict-flex-arrays=3).

Unlike struct acpi_nfit_flush_address and struct acpi_nfit_smbios, which
had their sizeof() uses adjusted in code, struct acpi_nfit_interleave did
not. This appears to have been a bug. After this change, there is a binary
difference in acpi_dm_dump_nfit() since the size of the structure now has
the correct size, as the prior result was including the trailing U32:

-       mov    $0x14,%ebp
+       mov    $0x10,%ebp

Link: https://github.com/acpica/acpica/commit/e66decc6
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Reviewed-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Tested-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: actbl2: Replace 1-element arrays with flexible arrays</title>
<updated>2023-04-06T18:29:11+00:00</updated>
<author>
<name>Kees Cook</name>
<email>kees@outflux.net</email>
</author>
<published>2023-04-05T13:50:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=74522fea27f8a0695f529089130da64ac98f1761'/>
<id>urn:sha1:74522fea27f8a0695f529089130da64ac98f1761</id>
<content type='text'>
ACPICA commit 44f1af0664599e87bebc3a1260692baa27b2f264

Similar to "Replace one-element array with flexible-array", replace the
1-element array with a proper flexible array member as defined by C99.

This allows the code to operate without tripping compile-time and run-
time bounds checkers (e.g. via __builtin_object_size(), -fsanitize=bounds,
and/or -fstrict-flex-arrays=3).

The sizeof() uses with struct acpi_nfit_flush_address and struct
acpi_nfit_smbios have been adjusted to drop the open-coded subtraction
of the trailing single element. The result is no binary differences in
.text nor .data sections.

Link: https://github.com/acpica/acpica/commit/44f1af06
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Co-developed-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: Add structure definitions for RISC-V RHCT</title>
<updated>2023-04-06T18:29:11+00:00</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2023-04-05T13:40:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=003567a3b70d0dc5adf71ca0b2bd43d2b4a1ee26'/>
<id>urn:sha1:003567a3b70d0dc5adf71ca0b2bd43d2b4a1ee26</id>
<content type='text'>
ACPICA commit 82afd0434e79f74b96a6be88115ddc8343a1ba40

RISC-V Hart Capabilities Table (RHCT) is a new static table.
The ECR to add RHCT is approved by the UEFI forum and will be
available in the next version of the ACPI spec.

Link: https://github.com/acpica/acpica/commit/82afd043
Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: MADT: Add RISC-V INTC interrupt controller</title>
<updated>2023-04-06T18:29:11+00:00</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2023-04-05T13:40:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f2ca92d08325b8d4668a6b3ee4b3d5622b75b952'/>
<id>urn:sha1:f2ca92d08325b8d4668a6b3ee4b3d5622b75b952</id>
<content type='text'>
ACPICA commit bd6d1ae1e13abe78e149c8b61b4bc7bc7feab015

The ECR to add RISC-V INTC interrupt controller is approved by
the UEFI forum and will be available in the next revision of
the ACPI specification.

Link: https://github.com/acpica/acpica/commit/bd6d1ae1
Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: Update all copyrights/signons to 2023</title>
<updated>2023-04-06T18:29:11+00:00</updated>
<author>
<name>Bob Moore</name>
<email>robert.moore@intel.com</email>
</author>
<published>2023-04-05T13:38:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=612c29328466bdc1454ce76959fc03a1e2f7087a'/>
<id>urn:sha1:612c29328466bdc1454ce76959fc03a1e2f7087a</id>
<content type='text'>
ACPICA commit 25bddd1824b1e450829468a64bbdcb38074ba3d2

Copyright updates to 2023.

Link: https://github.com/acpica/acpica/commit/25bddd18
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: Add support for Arm's MPAM ACPI table version 2</title>
<updated>2023-04-06T18:29:10+00:00</updated>
<author>
<name>Hesham Almatary</name>
<email>hesham.almatary@huawei.com</email>
</author>
<published>2023-04-05T13:37:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=47920aae34e295f4ffbeac0b10698ceda52eec99'/>
<id>urn:sha1:47920aae34e295f4ffbeac0b10698ceda52eec99</id>
<content type='text'>
ACPICA commit 005e24bcaa6e4c7db327b4f81fb63b2715aac7e6

Complies with ACPI for Memory System Resource Partitioning and
Monitoring 2.0 [1]. Document number: DEN0065, as of December 2022.

Support for all types of MPAM resources. No support yet for:
1) MPAM PCC Interface Type
2) The optional Resource-specific data per MSC node, introduced in v2 of the
MPAM ACPI spec.

[1] https://developer.arm.com/documentation/den0065/latest

Link: https://github.com/acpica/acpica/commit/005e24bc
Signed-off-by: Hesham Almatary &lt;hesham.almatary@huawei.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: ACPI 6.5: MADT: add support for trace buffer extension in GICC</title>
<updated>2023-04-06T18:29:10+00:00</updated>
<author>
<name>Xiongfeng Wang</name>
<email>wangxiongfeng2@huawei.com</email>
</author>
<published>2023-04-05T13:33:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=377421fcfb9716cbaef57dbc3d37ddeccd41f9fe'/>
<id>urn:sha1:377421fcfb9716cbaef57dbc3d37ddeccd41f9fe</id>
<content type='text'>
ACPICA commit 1363e35dc6976143d118588b5124d72017365588

Link: https://github.com/acpica/acpica/commit/1363e35d
Signed-off-by: Xiongfeng Wang &lt;wangxiongfeng2@huawei.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
</feed>
