<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/include/acpi/actbl1.h, branch linux-7.0.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.0.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.0.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2026-05-23T11:09:28+00:00</updated>
<entry>
<title>ACPICA: Provide #defines for EINJV2 error types</title>
<updated>2026-05-23T11:09:28+00:00</updated>
<author>
<name>Tony Luck</name>
<email>tony.luck@intel.com</email>
</author>
<published>2026-04-21T15:02:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d60bed8139ed0803ba528500ce22a14c653ed339'/>
<id>urn:sha1:d60bed8139ed0803ba528500ce22a14c653ed339</id>
<content type='text'>
[ Upstream commit 1f6008538384453eb4c13a3d7ff9e37ee8aee6b9 ]

EINJV2 defined new error types by moving the severity (correctable,
uncorrectable non-fatal, uncorrectable fatal) out of the "type".

ACPI 6.5 introduced EINJV2 and defined a vendor defined error type
using bit 31. This was dropped in ACPI 6.6.

Link: https://github.com/acpica/acpica/commit/e82d2d2fd145
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
Link: https://patch.msgid.link/20260421150216.11666-2-tony.luck@intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Stable-dep-of: 0c00cfbcfcff ("ACPI: APEI: EINJ: Fix EINJV2 memory error injection")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ACPICA: Refactor for TPR Base/Limit registers bitmasks</title>
<updated>2026-01-15T17:17:50+00:00</updated>
<author>
<name>Michal Camacho Romero</name>
<email>michal.camacho.romero@intel.com</email>
</author>
<published>2026-01-14T12:40:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e8f614dabd2238e462e4543abd1eb5c59e612836'/>
<id>urn:sha1:e8f614dabd2238e462e4543abd1eb5c59e612836</id>
<content type='text'>
Link: https://github.com/acpica/acpica/commit/5cb62a1d4970
Signed-off-by: Michal Camacho Romero &lt;michal.camacho.romero@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Link: https://patch.msgid.link/3193976.CbtlEUcBR6@rafael.j.wysocki
</content>
</entry>
<entry>
<title>ACPICA: Replace TPRn Base and Limit registers</title>
<updated>2026-01-15T17:17:50+00:00</updated>
<author>
<name>Michal Camacho Romero</name>
<email>michal.camacho.romero@intel.com</email>
</author>
<published>2026-01-14T12:39:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3b8907925a7964903955b59d974d98c7ae707d7a'/>
<id>urn:sha1:3b8907925a7964903955b59d974d98c7ae707d7a</id>
<content type='text'>
Replace TPRn Base and Limit registers with compatible bitmasks for them.

Link: https://github.com/acpica/acpica/commit/be91c5813936
Signed-off-by: Michal Camacho Romero &lt;michal.camacho.romero@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Link: https://patch.msgid.link/1871109.TLkxdtWsSY@rafael.j.wysocki
</content>
</entry>
<entry>
<title>ACPICA: Align comments in TPRn-related structures</title>
<updated>2026-01-15T17:17:50+00:00</updated>
<author>
<name>Michal Camacho Romero</name>
<email>michal.camacho.romero@intel.com</email>
</author>
<published>2026-01-14T12:37:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=691474b1ae63845044a28debe0e06b88a836770b'/>
<id>urn:sha1:691474b1ae63845044a28debe0e06b88a836770b</id>
<content type='text'>
Align comments in ACPI_TPRN_BASE_REG and ACPI_TPRN_LIMIT_REG structures.

Link: https://github.com/acpica/acpica/commit/95815d550969
Signed-off-by: Michal Camacho Romero &lt;michal.camacho.romero@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Link: https://patch.msgid.link/2286538.NgBsaNRSFp@rafael.j.wysocki
</content>
</entry>
<entry>
<title>ACPICA: Cleanup comments and DTPR Table handle functions</title>
<updated>2026-01-15T17:17:49+00:00</updated>
<author>
<name>Michal Camacho Romero</name>
<email>michal.camacho.romero@intel.com</email>
</author>
<published>2026-01-14T12:36:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9b02cf9ee67b284020d051da126694d555977e12'/>
<id>urn:sha1:9b02cf9ee67b284020d051da126694d555977e12</id>
<content type='text'>
Link: https://github.com/acpica/acpica/commit/cc480264335e
Signed-off-by: Michal Camacho Romero &lt;michal.camacho.romero@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Link: https://patch.msgid.link/2042656.yKVeVyVuyW@rafael.j.wysocki
</content>
</entry>
<entry>
<title>ACPICA: Verify DTPR and TPR Instance buffer pointers</title>
<updated>2026-01-15T17:17:49+00:00</updated>
<author>
<name>Michal Camacho Romero</name>
<email>michal.camacho.romero@intel.com</email>
</author>
<published>2026-01-14T12:35:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9565d4713ba6d3711d7b47fee9dde6725721ac06'/>
<id>urn:sha1:9565d4713ba6d3711d7b47fee9dde6725721ac06</id>
<content type='text'>
Verify DTPR and TPR Instance buffer pointers and refactor comments.

Link: https://github.com/acpica/acpica/commit/bdec5b61cf5b
Signed-off-by: Michal Camacho Romero &lt;michal.camacho.romero@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Link: https://patch.msgid.link/884204745.0ifERbkFSE@rafael.j.wysocki
</content>
</entry>
<entry>
<title>ACPICA: Fix Segmentation Fault error related to DTPR</title>
<updated>2026-01-15T17:17:49+00:00</updated>
<author>
<name>Michal Camacho Romero</name>
<email>michal.camacho.romero@intel.com</email>
</author>
<published>2026-01-14T12:34:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b110e28c3bf52c984c232ee633139ea10f754c0c'/>
<id>urn:sha1:b110e28c3bf52c984c232ee633139ea10f754c0c</id>
<content type='text'>
Fix Segmentation Fault error, caused by invalid buffer lenght in DTPR
Table Template:

 * Update buffer length for TPR Table, which invalid value caused
   Segmentation Fault, during ASL file production.

 * Refactor invalid values of TPR instances, arrays and serialization
   requests count and TPR Base addresses in the DTPR table template.

 * Fix offset updating in the acpi_dm_dump_dtpr function.

Link: https://github.com/acpica/acpica/commit/f75850bc4717
Signed-off-by: Michal Camacho Romero &lt;michal.camacho.romero@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Link: https://patch.msgid.link/2541195.jE0xQCEvom@rafael.j.wysocki
</content>
</entry>
<entry>
<title>ACPICA: Create auxiliary ACPI_TPR_AUX_SR structure for iASL compiler</title>
<updated>2026-01-15T17:17:49+00:00</updated>
<author>
<name>Michal Camacho Romero</name>
<email>michal.camacho.romero@intel.com</email>
</author>
<published>2026-01-14T12:33:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6f99d3fe224feefabc012869e10cbff52eb5f5f8'/>
<id>urn:sha1:6f99d3fe224feefabc012869e10cbff52eb5f5f8</id>
<content type='text'>
Define unofficial structure ACPI_TPR_AUX_SR, which holds information
about the number of serialization registers for TPRs.

It simplifies DTPR Serialization Request Info Table compilation.

Link: https://github.com/acpica/acpica/commit/31f470e708a9
Signed-off-by: Michal Camacho Romero &lt;michal.camacho.romero@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Link: https://patch.msgid.link/2266165.Icojqenx9y@rafael.j.wysocki
</content>
</entry>
<entry>
<title>ACPICA: Define DTPR structure related info tables and data template</title>
<updated>2026-01-15T17:17:48+00:00</updated>
<author>
<name>Michal Camacho Romero</name>
<email>michal.camacho.romero@intel.com</email>
</author>
<published>2026-01-14T12:24:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=30c2a333aa90c4265bed7629980eb0df72f56dfb'/>
<id>urn:sha1:30c2a333aa90c4265bed7629980eb0df72f56dfb</id>
<content type='text'>
 * DTPR Table Info
 * TPR Instance Table Info
 * TPR Array Table Info
 * TPR Serialize Request Table Info
 * DTPR Table Data Template

Link: https://github.com/acpica/acpica/commit/abadf1d34732
Signed-off-by: Michal Camacho Romero &lt;michal.camacho.romero@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Link: https://patch.msgid.link/3676546.iIbC2pHGDl@rafael.j.wysocki
</content>
</entry>
<entry>
<title>ACPICA: Add DTPR table support for the ASL compiler</title>
<updated>2026-01-15T17:17:48+00:00</updated>
<author>
<name>Michal Camacho Romero</name>
<email>michal.camacho.romero@intel.com</email>
</author>
<published>2026-01-14T12:23:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c5ecbc65bb2287b66b3b8adbdbe0fddb81bc297f'/>
<id>urn:sha1:c5ecbc65bb2287b66b3b8adbdbe0fddb81bc297f</id>
<content type='text'>
Define DTPR related structures offsets.

Link: https://github.com/acpica/acpica/commit/c6fc16c8936d
Signed-off-by: Michal Camacho Romero &lt;michal.camacho.romero@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Link: https://patch.msgid.link/7902293.EvYhyI6sBW@rafael.j.wysocki
</content>
</entry>
</feed>
