kernel/linux.git/drivers, branch v3.16.4

clk: qcom: Fix PLL rate configurations

2014-10-05T20:41:12+00:00

commit 5b6b7490af110c2b0df807eddd00ae6290bcf50a upstream. Sometimes we need to program PLLs with a fixed rate configuration during driver probe. Doing this after we register the PLLs with the clock framework causes the common clock framework to assume the rate of the PLLs are 0. This causes all sorts of problems for rate recalculations because the common clock framework caches the rate once at registration time unless a flag is set to always recalculate the rates. Split the qcom_cc_probe() function into two pieces, map and everything else, so that drivers which need to configure some PLL rates or otherwise twiddle bits in the clock controller can do so before registering clocks. This allows us to properly detect the rates of PLLs that are programmed at boot. Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code" Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: qcom: mdp_lut_clk is a child of mdp_src

2014-10-05T20:41:12+00:00

commit f87dfcabc6f173cc811d185d33327f50a8c88399 upstream. The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the child of the mdp_src clock. Fix it. Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: qcom: Fix MN frequency tables, parent map, and jpegd

2014-10-05T20:41:12+00:00

commit ff20783f7b9f35b29e768d8ecc7076c1ca1a60ca upstream. Clocks that don't have a pre-divider don't list any pre-divider in their frequency tables, but their tables are initialized using aggregate initializers. Use tagged initializers so we properly assign the m and n values for each frequency. Furthermore, the mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second element to pll2 instead of pll8, causing the clock driver to recalculate the wrong rate for any clocks using this array along with a rate that uses pll2. Plus the .num_parents field is 3 instead of 4 so you can't even switch the parent to pll3. Finally I noticed that the jpegd clock improperly indicates that the pre-divider width is only 2, when it's actually 4 bits wide. Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Tested-by: Rob Clark Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

staging/lustre: disable virtual block device for 64K pages

2014-10-05T20:41:12+00:00

commit 0bf22be0da8ea74bc7ccc5b07d7855830be16eca upstream. The lustre virtual block device cannot handle 64K pages and fails at compile time. To avoid running into this error, let's disable the Kconfig option for this driver in cases it doesn't support. Reported-by: Dann Frazier Signed-off-by: Arnd Bergmann Signed-off-by: Greg Kroah-Hartman

ahci_xgene: Removing NCQ support from the APM X-Gene SoC AHCI SATA Host Controller driver.

2014-10-05T20:41:12+00:00

commit 72f79f9e35bd3f78ee8853f2fcacaa197d23ebac upstream. This patch removes the NCQ support from the APM X-Gene SoC AHCI Host Controller driver as it doesn't support it. Signed-off-by: Loc Ho Signed-off-by: Suman Tripathi Signed-off-by: Tejun Heo [bwh: Backported to 3.16: host flags are passed to ahci_platform_init_host()] Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman

clk: ti: divider: Provide error check for incoming parameters in set_rate

2014-10-05T20:41:12+00:00

commit 2f1032517623b70920d99529e5c87c8c680ab8bf upstream. Check for valid parameters in check rate. Else, we end up getting errors like: [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc1 #1 [ 0.000000] [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack) from [] (dump_stack+0x78/0x94) [ 0.000000] [] (dump_stack) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0) from [] (ti_clk_divider_set_rate+0x14/0x14c) [ 0.000000] [] (ti_clk_divider_set_rate) from [] (clk_change_rate+0x138/0x180) [ 0.000000] [] (clk_change_rate) from [] (clk_change_rate+0x108/0x180) This occurs as part of the inital clock tree update of child clock nodes where new_rate could be 0 for non functional clocks. Fixes: b4761198bfaf296 ("CLK: ti: add support for ti divider-clock") Signed-off-by: Nishanth Menon Signed-off-by: Tero Kristo Signed-off-by: Greg Kroah-Hartman

clk: prevent erronous parsing of children during rate change

2014-10-05T20:41:12+00:00

commit 067bb1741c27c8d3b74ac98c0b8fc12b31e67005 upstream. In some cases, clocks can switch their parent with clk_set_rate, for example clk_mux can do this in some cases. Current implementation of clk_change_rate uses un-safe list iteration on the clock children, which will cause wrong clocks to be parsed in case any of the clock children change their parents during the change rate operation. Fixed by using the safe list iterator instead. The problem was detected due to some divide by zero errors generated by clock init on dra7-evm board, see discussion under http://article.gmane.org/gmane.linux.ports.arm.kernel/349180 for details. Fixes: 71472c0c06cf ("clk: add support for clock reparent on set_rate") Signed-off-by: Tero Kristo Reported-by: Nishanth Menon Signed-off-by: Mike Turquette Signed-off-by: Greg Kroah-Hartman

clk: ti: dra7-atl: Provide error check for incoming parameters in set_rate

2014-10-05T20:41:11+00:00

commit 20411dad75ece9a613af715df4489e60990c4017 upstream. Check for valid parameters in check rate. Else, we end up getting errors. This occurs as part of the inital clock tree update of child clock nodes where new_rate could be 0 for non functional clocks. Fixes: 9ac33b0ce81fa48 (" CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Signed-off-by: Nishanth Menon Signed-off-by: Tero Kristo Signed-off-by: Greg Kroah-Hartman

cpufreq: update 'cpufreq_suspended' after stopping governors

2014-10-05T20:41:11+00:00

commit b1b12babe3b72cfb08b875245e5a5d7c2747c772 upstream. Commit 8e30444e1530 ("cpufreq: fix cpufreq suspend/resume for intel_pstate") introduced a bug where the governors wouldn't be stopped anymore for ->target{_index}() drivers during suspend. This happens because 'cpufreq_suspended' is updated before stopping the governors during suspend and due to this __cpufreq_governor() would return early due to this check: /* Don't start any governor operations if we are entering suspend */ if (cpufreq_suspended) return 0; Fixes: 8e30444e1530 ("cpufreq: fix cpufreq suspend/resume for intel_pstate") Signed-off-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman

dmaengine: dw: don't perform DMA when dmaengine_submit is called

2014-10-05T20:41:11+00:00

commit dd8ecfcac66b4485416b2d1df0ec4798b198d7d6 upstream. Accordingly to discussion [1] and followed up documentation the DMA controller driver shouldn't start any DMA operations when dmaengine_submit() is called. This patch fixes the workflow in dw_dmac driver to follow the documentation. [1] http://www.spinics.net/lists/arm-kernel/msg125987.html Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul Cc: "Petallo, MauriceX R" Signed-off-by: Greg Kroah-Hartman