kernel/linux.git/drivers/tty/serial/imx.c, branch v6.3.2

serial: imx: remove a redundant check

2023-02-16T12:50:31+00:00

cpp_check reports drivers/tty/serial/imx.c:1207:15: style: Condition 'r_bytes>0' is always true [knownConditionTrueFalse] if (r_bytes > 0) { r_byte is set to r_bytes = rx_ring->head - rx_ring->tail; The head - tail calculation is also done by the earlier check if (rx_ring->head <= sg_dma_len(sgl) && rx_ring->head > rx_ring->tail) { so r_bytes will always be > 0, so the second check is not needed. Signed-off-by: Tom Rix Reviewed-by: Iuliana Prodan Link: https://lore.kernel.org/r/20230211154550.2130670-1-trix@redhat.com Signed-off-by: Greg Kroah-Hartman

serial: imx: get rid of registers shadowing

2023-02-08T12:15:10+00:00

Neither registers shadowing is functionally needed as all the registers are read-write, nor the shadowing makes much sense for speed-up, as most speed critical reads/writes (of data Rx/Tx registers) are not shadowed anyway. Moreover, the shadowing code is obviously pure overhead on the write path. Get rid of the shadowing code and variables due to above considerations. Signed-off-by: Sergey Organov Link: https://lore.kernel.org/r/20230201141603.4205-1-sorganov@gmail.com Signed-off-by: Greg Kroah-Hartman

serial: imx: refine local variables in rxint()

2023-02-08T12:12:07+00:00

The 'rx' is chip register, similar to 'usr2', so let it be of 'u32' type as well. Move 'flg' to be FIFO read loop local as it's not used outside. Signed-off-by: Sergey Organov Link: https://lore.kernel.org/r/20230201142700.4346-8-sorganov@gmail.com Signed-off-by: Greg Kroah-Hartman

serial: imx: stop using USR2 in FIFO reading loop

2023-02-08T12:12:05+00:00

The chip provides all the needed bits in the URXD0 register that we read anyway for data, so get rid of reading USR2 and use only URXD0 bits instead. Signed-off-by: Sergey Organov Link: https://lore.kernel.org/r/20230201142700.4346-7-sorganov@gmail.com Signed-off-by: Greg Kroah-Hartman

serial: imx: remove redundant USR2 read from FIFO reading loop

2023-02-08T12:12:02+00:00

There is no need to read USR2 twice at every loop iteration: get rid of the second read. Signed-off-by: Sergey Organov Link: https://lore.kernel.org/r/20230201142700.4346-6-sorganov@gmail.com Signed-off-by: Greg Kroah-Hartman

serial: imx: do not break from FIFO reading loop prematurely

2023-02-08T12:11:58+00:00

There is no reason to prematurely break out of FIFO reading loop, and it might cause needless reenters into ISR, so keep reading until FIFO is empty. Signed-off-by: Sergey Organov Link: https://lore.kernel.org/r/20230201142700.4346-5-sorganov@gmail.com Signed-off-by: Greg Kroah-Hartman

serial: imx: do not sysrq broken chars

2023-02-08T12:11:55+00:00

Do not call uart_handle_sysrq_char() if we got any receive error along with the character, as we don't want random junk to be considered a sysrq. Signed-off-by: Sergey Organov Link: https://lore.kernel.org/r/20230201142700.4346-4-sorganov@gmail.com Signed-off-by: Greg Kroah-Hartman

serial: imx: work-around for hardware RX flood

2023-02-08T12:11:52+00:00

Check if hardware Rx flood is in progress, and issue soft reset to UART to stop the flood. A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of cases this starts a flood of "receiving" of 0xff characters by the iMX UART that is terminated by any activity on RxD line, or could be stopped by issuing soft reset to the UART (just stop/start of RX does not help). Note that in essence what we did here is sending isolated start bit about 2.4 times shorter than it is to be if issued on the UART configured baud rate. There was earlier attempt to fix similar issue in: 'commit b38cb7d25711 ("serial: imx: Disable new features of autobaud detection")', but apparently it only gets harder to reproduce the issue after that commit. Signed-off-by: Sergey Organov Link: https://lore.kernel.org/r/20230201142700.4346-3-sorganov@gmail.com Signed-off-by: Greg Kroah-Hartman

serial: imx: factor-out common code to imx_uart_soft_reset()

2023-02-08T12:11:48+00:00

We perform soft reset in 2 places, slightly differently for no sufficient reasons, so move more generic variant to a function, and re-use the code. Out of 2 repeat counters, 10 and 100, select 10, as the code works at interrupts disabled, and in practice the reset happens immediately. Signed-off-by: Sergey Organov Link: https://lore.kernel.org/r/20230201142700.4346-2-sorganov@gmail.com Signed-off-by: Greg Kroah-Hartman

tty: serial: imx: disable Ageing Timer interrupt request irq

2023-02-08T12:09:00+00:00

There maybe pending USR interrupt before requesting irq, however uart_add_one_port has not executed, so there will be kernel panic: [ 0.795668] Unable to handle kernel NULL pointer dereference at virtual addre ss 0000000000000080 [ 0.802701] Mem abort info: [ 0.805367] ESR = 0x0000000096000004 [ 0.808950] EC = 0x25: DABT (current EL), IL = 32 bits [ 0.814033] SET = 0, FnV = 0 [ 0.816950] EA = 0, S1PTW = 0 [ 0.819950] FSC = 0x04: level 0 translation fault [ 0.824617] Data abort info: [ 0.827367] ISV = 0, ISS = 0x00000004 [ 0.831033] CM = 0, WnR = 0 [ 0.833866] [0000000000000080] user address but active_mm is swapper [ 0.839951] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP [ 0.845953] Modules linked in: [ 0.848869] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.1.1+g56321e101aca #1 [ 0.855617] Hardware name: Freescale i.MX8MP EVK (DT) [ 0.860452] pstate: 000000c5 (nzcv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 0.867117] pc : __imx_uart_rxint.constprop.0+0x11c/0x2c0 [ 0.872283] lr : imx_uart_int+0xf8/0x1ec The issue only happends in the inmate linux when Jailhouse hypervisor enabled. The test procedure is: while true; do jailhouse enable imx8mp.cell jailhouse cell linux xxxx sleep 10 jailhouse cell destroy 1 jailhouse disable sleep 5 done And during the upper test, press keys to the 2nd linux console. When `jailhouse cell destroy 1`, the 2nd linux has no chance to put the uart to a quiese state, so USR1/2 may has pending interrupts. Then when `jailhosue cell linux xx` to start 2nd linux again, the issue trigger. In order to disable irqs before requesting them, both UCR1 and UCR2 irqs should be disabled, so here fix that, disable the Ageing Timer interrupt in UCR2 as UCR1 does. Fixes: 8a61f0c70ae6 ("serial: imx: Disable irqs before requesting them") Suggested-by: Sherry Sun Reviewed-by: Sherry Sun Signed-off-by: Peng Fan Acked-by: Jason Liu Link: https://lore.kernel.org/r/20230206013016.29352-1-sherry.sun@nxp.com Signed-off-by: Greg Kroah-Hartman