kernel/linux.git/drivers/tty/serial/8250/Makefile, branch linux-4.4.y

serial: 8250_pci: Intel MID UART support to its own driver

2015-10-18T04:18:38+00:00

Intel MID UART quirks require already quite a bit of code in 8250_pci.c. On new Intel platforms where it is used, the integrated DMA engine no longer has its own PCI device, but is instead configured from the UART's MMIO. That means we will have to add even more code for handling just MID UARTs. Instead of adding that to 8250_pci.c, splitting the support of Intel MID UART into its own driver. Handling of the integrated DMA engine becomes much simpler this way. Own driver will also remove the need for things like specific set_termios hooks for every board using this UART, and simplify the handling of it in general. Signed-off-by: Heikki Krogerus Acked-by: Andy Shevchenko Signed-off-by: Greg Kroah-Hartman

serial: 8250: Split base port operations from universal driver

2015-07-24T00:43:01+00:00

Refactor base port operations into new file; 8250_port.c. Legacy irq handling, RSA port support, port storage for universal driver, driver definition, module parameters and linkage remain in 8250_core.c The source file split and resulting modules is diagrammed below: 8250_core.c ====> 8250_core.c __ \ \ \ +-- 8250.ko (alias 8250_core) \ 8250_pnp.c __/ (universal driver) \ => 8250_port.c __ \ +-- 8250_base.ko 8250_dma.c __/ (port operations) Signed-off-by: Peter Hurley Signed-off-by: Greg Kroah-Hartman

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

2015-06-27T19:44:34+00:00

Pull MIPS updates from Ralf Baechle: - Improvements to the tlb_dump code - KVM fixes - Add support for appended DTB - Minor improvements to the R12000 support - Minor improvements to the R12000 support - Various platform improvments for BCM47xx - The usual pile of minor cleanups - A number of BPF fixes and improvments - Some improvments to the support for R3000 and DECstations - Some improvments to the ATH79 platform support - A major patchset for the JZ4740 SOC adding support for the CI20 platform - Add support for the Pistachio SOC - Minor BMIPS/BCM63xx platform support improvments. - Avoid "SYNC 0" as memory barrier when unlocking spinlocks - Add support for the XWR-1750 board. - Paul's __cpuinit/__cpuinitdata cleanups. - New Malta CPU board support large memory so enable ZONE_DMA32. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits) MIPS: spinlock: Adjust arch_spin_lock back-off time MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA MIPS: BCM47xx: Simplify handling SPROM revisions MIPS: Cobalt Don't use module_init in non-modular MTD registration. MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/ MIPS: use for_each_sg() MIPS: BCM47xx: Don't select BCMA_HOST_PCI MIPS: BCM47xx: Add helper variable for storing NVRAM length MIPS: IRQ/IP27: Move IRQ allocation API to platform code. MIPS: Replace smp_mb with release barrier function in unlocks. MIPS: i8259: DT support MIPS: Malta: Basic DT plumbing MIPS: include errno.h for ENODEV in mips-cm.h MIPS: Define GCR_GIC_STATUS register fields MIPS: BPF: Introduce BPF ASM helpers MIPS: BPF: Use BPF register names to describe the ABI MIPS: BPF: Move register definition to the BPF header MIPS: net: BPF: Replace RSIZE with SZREG MIPS: BPF: Free up some callee-saved registers MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers ...

serial: 8250_ingenic: support for Ingenic SoC UARTs

2015-06-21T19:53:24+00:00

Introduce a driver suitable for use with the UARTs present in Ingenic SoCs such as the JZ4740 & JZ4780. These are described as being ns16550 compatible but aren't quite - they require the setting of an extra bit in the FCR register to enable the UART module. The serial_out implementation is the same as that in arch/mips/jz4740/serial.c - which will shortly be removed. Signed-off-by: Paul Burton Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: Lars-Peter Clausen Cc: linux-serial@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Sebastian Andrzej Siewior Cc: Peter Hurley Cc: Alan Cox Cc: linux-kernel@vger.kernel.org Cc: Matthias Brugger Cc: Ricardo Ribalda Delgado Cc: Tony Lindgren Cc: John Crispin Patchwork: https://patchwork.linux-mips.org/patch/10159/ Signed-off-by: Ralf Baechle

serial: 8250: add LPC18xx/43xx UART driver

2015-05-31T21:56:33+00:00

Serial port driver for the 8250-based UART found on LPC18xx/43xx devices. The UART is 16550A compatible with additional features like RS485 support, synchronous mode, IrDA, and DMA. For now only basic UART and RS485 operation is supported. Signed-off-by: Joachim Eastwood Signed-off-by: Greg Kroah-Hartman

serial: 8250_uniphier: add UniPhier serial driver

2015-05-31T21:55:13+00:00

Add the driver for on-chip UART used on UniPhier SoCs. This hardware is similar to 8250, but the register mapping is slightly different: - The offset to FCR, MCR is different. - The divisor latch access bit does not exist. Instead, the divisor latch register is available at offset 9. This driver overrides serial_{in,out}, dl_{read,write} callbacks, but wants to borrow most of code from 8250_core.c. Signed-off-by: Masahiro Yamada Reviewed-by: Matthias Brugger Signed-off-by: Greg Kroah-Hartman

tty: serial: Add 8250-core based omap driver

2014-11-06T03:05:13+00:00

This patch provides a 8250-core based UART driver for the internal OMAP UART. The long term goal is to provide the same functionality as the current OMAP uart driver and DMA support. I tried to merge omap-serial code together with the 8250-core code. There should should be hardly a noticable difference. The trigger levels are different compared to omap-serial: - omap serial TX: Interrupt comes after TX FIFO has room for 16 bytes. TX of 4096 bytes in one go results in 256 interrupts RX: Interrupt comes after there is on byte in the FIFO. RX of 4096 bytes results in 4096 interrupts. - this driver TX: Interrupt comes once the TX FIFO is empty. TX of 4096 bytes results in 65 interrupts. That means there will be gaps on the line while the driver reloads the FIFO. RX: Interrupt comes once there are 48 bytes in the FIFO or less over "longer" time frame. We have 1 / 11520 * 10^3 * 16 => 1.38… ms 1.38ms to react and purge the FIFO on 115200,8N1. Since the other driver fired after each byte it had ~5.47ms time to react. This _may_ cause problems if one relies on no missing bytes and has no flow control. On the other hand we get only 85 interrupts for the same amount of data. It has been only tested as console UART on am335x-evm, dra7-evm and beagle bone. I also did some longer raw-transfers to meassure the load. The device name is ttyS based instead of ttyO. If a ttyO based node name is required please ask udev for it. If both driver are activated (this and omap-serial) then this serial driver will take control over the device due to the link order v9…v10: - Tony noticed that omap3 won't show anything after waking up from core off. In v9 I reworked the register restore and set IER to 0 by accident. This went unnoticed because start_tx usually sets ier (either due to DMA bug or due to TX-complete IRQ). - dropped EFR and SLEEP from capabilities. We do have both but nobody should touch it. We already handle SLEEP ourself. - make the private copy of the registers (like EFR) u8 instead u32 - drop MDR1 & DL[ML] reset in restore registers. Does not look required it is set to the required value later. - update MDR1 & SCR only if changed. - set MDR1 as the last thing. The errata says that we should setup everything before MDR1 set. - avoid div by 0 in omap_8250_get_divisor() if baud rate gets very large (Frans Klaver fixed the same thing omap-serial) - drop "is in early stage" from Kconfig. v8…v9: - less on a file seems to hang the am335x after a while. I believe I introduce this bug a while ago since I can reproduce this prior to v8. Fixed by redoing the omap8250_restore_regs() v7…v8: - redo the register write. There is now one function for that which is used from set_termios() and runtime-resume. - drop PORT_OMAP_16750 and move the setup to the omap file. We have our own set termios function anyway (Heikki Krogerus) - use MEM instead of MEM32. TRM of AM/DM37x says that 32bit access on THR might result in data abort. We only need 32bit access in the errata function which is before we use 8250's read function so it doesn't matter. v4…v7: - change trigger levels after some tests with raw transfers. v3…v4: - drop RS485 support - wire up ->throttle / ->unthrottle v2…v3: - wire up startup & shutdown for wakeup-irq handling. - RS485 handling (well the core does). v1…v2: - added runtime PM. Could somebody could please double check this? - added omap_8250_set_termios() Reviewed-by: Tony Lindgren Tested-by: Tony Lindgren Tested-by: Frans Klaver Signed-off-by: Sebastian Andrzej Siewior Reviewed-by: Peter Hurley Signed-off-by: Greg Kroah-Hartman

tty: serial: 8250: Add Mediatek UART driver

2014-09-10T13:59:41+00:00

The device has a highspeed register which influences the calcualtion of the divisor. The chip lacks support for some baudrates. When requested, we set the divisor to the next smaller baudrate and adjust the c_cflag accordingly. Signed-off-by: Matthias Brugger Reviewed-by: Alan Cox Signed-off-by: Greg Kroah-Hartman

serial: Add support for Fintek F81216A LPC to 4 UART

2014-09-08T22:26:26+00:00

This patch lets you set the RS485 cappabilites of the device through TIOCSRS485 and TIOCGRS485 as defined on Documentation/serial/serial-rs485.txt In order to probe the device, the PNP id and the device id is used. Signed-off-by: Ricardo Ribalda Delgado Signed-off-by: Greg Kroah-Hartman

TTY: 8250, revert module name change

2013-03-25T23:26:23+00:00

In 3.7 the 8250 module name was changed unintentionally from 8250 to 8250_core by commit 835d844d1a28efba81d5aca7385e24c29d3a6db2 (8250_pnp: do pnp probe before legacy probe). We then had to re-introduce the old module options to ensure the old good 8250.nr_uart & co. still work. This can be done only by a very dirty hack and we did it in f2b8dfd9e480c3db3bad0c25c590a5d11b31f4ef (serial: 8250: Keep 8250. module options functional after driver rename). That is so damn ugly so that I decided to revert to the old module name and deprecate the new 8250_core options present in 3.7 and 3.8 only. The deprecation will happen in the following patch. Note that this patch changes the hack above to support "8250_core.*", because we now have "8250.*" natively. Signed-off-by: Jiri Slaby Cc: Josh Boyer Signed-off-by: Greg Kroah-Hartman