kernel/linux.git/drivers/staging/axis-fifo, branch v4.19.16

staging: fix platform_no_drv_owner.cocci warnings

2018-07-29T12:40:41+00:00

drivers/staging/axis-fifo/axis-fifo.c:1081:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Fixes: 4a965c5f89de ("staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core") CC: Jacob Feder Signed-off-by: kbuild test robot Signed-off-by: Greg Kroah-Hartman

staging: axis-fifo: fix return value check in axis_fifo_probe()

2018-07-28T07:26:31+00:00

In case of error, the function device_create() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: 4a965c5f89de ("staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core") Signed-off-by: Wei Yongjun Signed-off-by: Greg Kroah-Hartman

staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core

2018-07-24T12:14:13+00:00

This IP core has read and write AXI-Stream FIFOs, the contents of which can be accessed from the AXI4 memory-mapped interface. This is useful for transferring data from a processor into the FPGA fabric. The driver creates a character device that can be read/written to with standard open/read/write/close. See Xilinx PG080 document for IP details. https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf The driver currently supports only store-forward mode with a 32-bit AXI4 Lite interface. DOES NOT support: - cut-through mode - AXI4 (non-lite) Signed-off-by: Jacob Feder Signed-off-by: Greg Kroah-Hartman