kernel/linux.git/drivers/spi/spi-intel.c, branch v7.1

spi: intel: Add support for 128M component density

2025-10-20T15:15:29+00:00

With the recent hardware the flash component density can be increased to 128M. Update the driver to support this. While there log a warning if we encounter an unsupported value in this field. Signed-off-by: Mika Westerberg Link: https://patch.msgid.link/20251020145415.3377022-2-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown

spi: intel: Allow writeable MTD partition with module param

2025-07-25T12:44:36+00:00

The MTD device is blocked from writing to the SPI-NOR chip if any region of it is write-protected, even if "writeable=1" module parameter is set. Add ability to bypass this behaviour by introducing new module parameter "ignore_protestion_status" which allows to rely on the write protection mechanism of SPI-NOR chip itself, which most modern chips (since the 1990'+) have already implemented. Any erase/write operations performed on the write-protected section will be rejected by the chip. Signed-off-by: Jakub Czapiga Link: https://patch.msgid.link/20250725122542.2633334-1-czapiga@google.com Signed-off-by: Mark Brown

spi: intel: Improve resource mapping

2025-04-24T11:56:59+00:00

Let's use the pci/platform-specialized functions for mapping a resource, and pass the mapped address to intel_spi_probe. Benefits are: - No separate call needed for getting the resource, and no access to struct pci_dev internals (pdev->resource[]). - More user-friendly output in /proc/iomem. In my case: before 80704000-80704fff : 0000:00:1f.5 80704000-80704fff : 0000:00:1f.5 0000:00:1f.5 after 80704000-80704fff : 0000:00:1f.5 80704000-80704fff : spi_intel_pci Signed-off-by: Heiner Kallweit Link: https://patch.msgid.link/2585fa05-60c4-48c4-a838-e87014665ae2@gmail.com Signed-off-by: Mark Brown

spi: intel: Add protected and locked attributes

2024-10-09T13:41:00+00:00

The manufacturing access to the PCH/SoC SPI device is traditionally performed via userspace driver accessing registers via /dev/mem but due to security concerns /dev/mem access is being much restricted, hence the reason for utilizing dedicated Intel PCH/SoC SPI controller driver, which is already implemented in the Linux kernel. Intel PCH/SoC SPI controller protects the flash storage via two mechanisms one is the via region protection registers and second via BIOS lock. The BIOS locks only the BIOS regions usually 0 and/or 6. The device always boots with BIOS lock set, but during manufacturing the BIOS lock has to be lifted in order to enable the write access. This can be done by passing "writeable=1" in the command line when the driver is loaded. This "locked" state is exposed through new sysfs attributes (intel_spi_locked, intel_spi_bios_locked). Second, also the region protection status is exposed via sysfs attribute (intel_spi_protected) as the manufacturing will need the both files in order to validate that the device is properly sealed. Includes code written by Tamar Mashiah. Signed-off-by: Alexander Usyskin Co-developed-by: Tomas Winkler Signed-off-by: Tomas Winkler Reviewed-by: Andy Shevchenko Signed-off-by: Mika Westerberg Link: https://patch.msgid.link/20241009062244.2436793-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown

spi: intel: Add check devm_kasprintf() returned value

2024-08-30T11:28:17+00:00

intel_spi_populate_chip() use devm_kasprintf() to set pdata->name. This can return a NULL pointer on failure but this returned value is not checked. Fixes: e58db3bcd93b ("spi: intel: Add default partition and name to the second chip") Signed-off-by: Charles Han Reviewed-by: Mika Westerberg Link: https://patch.msgid.link/20240830074106.8744-1-hanchunchao@inspur.com Signed-off-by: Mark Brown

spi: intel: Keep the BIOS partition inside the first chip

2024-02-05T14:35:47+00:00

If there are two flash chips connected flash regions can refer to the second chip too. In this case we may see the following warning: mtd: partition "BIOS" extends beyond the end of device "0000:00:1f.5" -- size truncated to 0x400000 For this reason, check the BIOS partition size against the chip size and make sure it stays within the that. Signed-off-by: Mika Westerberg Link: https://lore.kernel.org/r/20240201121638.207632-2-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown

spi: intel: Add default partition and name to the second chip

2024-02-05T14:35:46+00:00

This should make it easier to identify the second chip and also allows using "mtdparts=" and the like with this chip too. Signed-off-by: Mika Westerberg Link: https://lore.kernel.org/r/20240201121638.207632-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown

spi: intel: make mem_ops comparison unique to opcode match

2023-11-18T12:36:34+00:00

Instead of comparing parameters for every supported mem_ops, only compare on opcode match, which is relatively more efficient. Signed-off-by: Raag Jadav Reviewed-by: Mika Westerberg Link: https://lore.kernel.org/r/20231117144053.24005-1-raag.jadav@intel.com Signed-off-by: Mark Brown

spi: intel: switch to use modern name

2023-08-14T12:11:04+00:00

Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang Link: https://lore.kernel.org/r/20230807124105.3429709-19-yangyingliang@huawei.com Signed-off-by: Mark Brown

spi: Replace all spi->chip_select and spi->cs_gpiod references with function call

2023-03-11T12:34:01+00:00

Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively. Signed-off-by: Amit Kumar Mahapatra Acked-by: Heiko Stuebner # Rockchip drivers Reviewed-by: Michal Simek Reviewed-by: Cédric Le Goater # Aspeed driver Reviewed-by: Dhruva Gole # SPI Cadence QSPI Reviewed-by: Patrice Chotard # spi-stm32-qspi Acked-by: William Zhang # bcm63xx-hsspi driver Reviewed-by: Serge Semin # DW SSI part Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org Signed-off-by: Mark Brown