kernel/linux.git/drivers/spi/Makefile, branch v4.11.5

spi: lantiq-ssc: add support for Lantiq SSC SPI controller

2017-02-14T17:10:40+00:00

This driver supports the Lantiq SSC SPI controller in master mode. This controller is found on Intel (former Lantiq) SoCs like the Danube, Falcon, xRX200, xRX300. The hardware uses two hardware FIFOs one for received and one for transferred bytes. When the driver writes data into the transmit FIFO the complete word is taken from the FIFO into a shift register. The data from this shift register is then written to the wire. This driver uses the interrupts signaling the status of the FIFOs and not the shift register. It is also possible to use the interrupts for the shift register, but they will send a signal after every word. When using the interrupts for the shift register we get a signal when the last word is written into the shift register and not when it is written to the wire. After all FIFOs are empty the driver busy waits till the hardware is not busy any more and returns the transfer status. Signed-off-by: Daniel Schwierzeck Signed-off-by: Hauke Mehrtens Signed-off-by: Mark Brown

Merge remote-tracking branches 'spi/topic/fsl-lpspi', 'spi/topic/imx', 'spi/topic/jcore' and 'spi/topic/omap' into spi-next

2016-12-12T15:54:14+00:00

spi: Add support for Armada 3700 SPI Controller

2016-12-08T16:05:34+00:00

Marvell Armada 3700 SoC comprises an SPI Controller. This Controller supports up to 4 SPI slave devices, with dedicated chip selects,supports SPI mode 0/1/2 and 3, CPIO or Fifo mode with DMA transfers and different SPI transfer mode (Single, Dual or Quad). This commit adds basic driver support for FIFO mode. In this mode, dedicated registers are used to store the instruction, the address, the read mode and the data. Write and Read FIFO are used to store the outcoming or incoming data. The data FIFOs are accessible via DMA or by the CPU. Only the CPU is supported for now. Signed-off-by: Romain Perier Tested-by: Gregory CLEMENT Signed-off-by: Mark Brown

spi: imx: add lpspi bus driver

2016-11-22T19:13:16+00:00

This patch adds lpspi driver to support new i.MX products which use lpspi instead of ecspi. The lpspi can continue operating in stop mode when an appropriate clock is available. It is also designed for low CPU overhead with DMA offloading of FIFO register accesses. Signed-off-by: Gao Pan Reviewed-by: Fugang Duan Signed-off-by: Mark Brown

Merge remote-tracking branches 'spi/topic/octeon', 'spi/topic/pic32-sqi', 'spi/topic/pxa2xx' and 'spi/topic/qup' into spi-next

2016-09-30T16:14:14+00:00

Merge remote-tracking branches 'spi/topic/fsl-espi', 'spi/topic/imx', 'spi/topic/jcore', 'spi/topic/loopback' and 'spi/topic/meson' into spi-next

2016-09-30T16:14:10+00:00

spi: iproc-qspi: Add Broadcom iProc SoCs support

2016-09-24T19:03:25+00:00

This spi driver uses the common spi-bcm-qspi driver and implements iProc SoCs specific interrupt controller. The common driver now calls the SoC handlers when present. Adding support for both muxed l1 and unmuxed interrupt sources. Signed-off-by: Kamal Dasu Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Mark Brown

spi: brcmstb-qspi: Broadcom settop platform driver

2016-09-14T17:03:32+00:00

Adding the settop SoC platfrom driver, this driver is compatible with the settop MSPI+BSPI and MSPI only blocks implemented on the SoCs. Driver calls the spi-bcm-qspi probe(), remove() and pm_ops. Signed-off-by: Kamal Dasu Signed-off-by: Mark Brown

spi: bcm-qspi: Add Broadcom MSPI driver

2016-09-14T17:03:32+00:00

Master SPI driver for Broadcom settop, iProc SoCs. The driver is used for devices that use SPI protocol on BRCMSTB, NSP, NS2 SoCs. SoC platform driver call exported porbe(), remove() and suspend/resume pm_ops implemented in this common driver. Signed-off-by: Kamal Dasu Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Mark Brown

spi: octeon: Add ThunderX driver

2016-08-19T15:24:39+00:00

Add ThunderX SPI driver using the shared part from the Octeon driver. The main difference of the ThunderX driver is that it is a PCI device so probing is different. The system clock settings can be specified in device tree. Signed-off-by: Jan Glauber Signed-off-by: Mark Brown