kernel/linux.git/drivers/soundwire/intel.h, branch v6.19.11

soundwire: intel: Add awareness of ACE3+ microphone privacy

2025-05-14T11:43:25+00:00

ACE3 introduced microphone privacy and along this feature it adds a new register in vendor specific SHIM to control and status reporting. The control of mic privacy via the SHIM register is only to enable the interrupt generation via soundwire, but not handled by the soundwire code as the mic privacy is not a feature of the soundwire IP. On the other hand, printing the register value brings value for debugging, so add a new flag to allow this conditionally. Signed-off-by: Peter Ujfalusi Reviewed-by: Ranjani Sridharan Signed-off-by: Bard Liao Link: https://lore.kernel.org/r/20250430074714.94000-2-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul

soundwire: intel: add BPT context definition

2025-03-10T07:01:19+00:00

This is needed to be shared between open/send_async/close. Signed-off-by: Pierre-Louis Bossart Signed-off-by: Bard Liao Reviewed-by: Péter Ujfalusi Reviewed-by: Liam Girdwood Reviewed-by: Ranjani Sridharan Tested-by: shumingf@realtek.com Link: https://lore.kernel.org/r/20250227140615.8147-13-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul

Merge tag 'soundwire-6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire

2024-09-23T21:00:46+00:00

Pull soundwire updates from Vinod Koul: - bus cleanup for warnings and probe deferral errors suppression - cadence recheck for status with a delayed work - intel interrupt rework on reset exit * tag 'soundwire-6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire: soundwire: intel_bus_common: enable interrupts before exiting reset soundwire: cadence: re-check Peripheral status with delayed_work soundwire: bus: clean up probe warnings soundwire: bus: drop unused driver name field soundwire: bus: suppress probe deferral errors

soundwire: intel: add probe-time check on link id

2024-08-19T11:25:52+00:00

In older platforms, the number of links was constant and hard-coded to 4. Newer platforms can have varying number of links, so we need to add a probe-time check to make sure the ACPI-reported information with _DSD properties is aligned with hardware capabilities reported in the SoundWire LCAP register. Acked-by: Vinod Koul Signed-off-by: Pierre-Louis Bossart Reviewed-by: Péter Ujfalusi Signed-off-by: Bard Liao Acked-by: Mark Brown Reviewed-by: Takashi Iwai Link: https://patch.msgid.link/20240819005548.5867-3-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown

soundwire: cadence: re-check Peripheral status with delayed_work

2024-08-18T06:44:24+00:00

The SoundWire peripheral enumeration is entirely based on interrupts, more specifically sticky bits tracking state changes. This patch adds a defensive programming check on the actual status reported in PING frames. If for some reason an interrupt was lost or delayed, the delayed work would detect a peripheral change of status after the bus starts. The 100ms defined for the delay is not completely arbitrary, if a Peripheral didn't join the bus within that delay then probably the hardware link is broken, and conversely if the detection didn't happen because of software issues the 100ms is still acceptable in terms of user experience. The overhead of the one-shot workqueue is minimal, and the mutual exclusion ensures that the interrupt and delayed work cannot update the status concurrently. Reviewed-by: Liam Girdwood Signed-off-by: Pierre-Louis Bossart Signed-off-by: Bard Liao Link: https://lore.kernel.org/r/20240805114921.88007-1-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul

soundwire: intel_ace2.x: add AC timing extensions for PantherLake

2024-06-03T12:11:11+00:00

The ACE3 IP used in PantherLake exposes new bitfields in the ACTMCTL register to better control clocks/delays. These bitfields were reserved/zero in the ACE2.x IP, to simplify the integration the new bifields are added unconditionally. The behavior will only be impacted when the firmware exposes DSD properties to set non-zero values. Signed-off-by: Pierre-Louis Bossart Reviewed-by: Péter Ujfalusi Reviewed-by: Ranjani Sridharan Signed-off-by: Bard Liao Link: https://lore.kernel.org/r/20240603070240.5165-1-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul

soundwire: intel_ace2.x: add support for DOAISE property

2024-05-04T12:56:50+00:00

Extend previous patches with the DOAISE field and property. Signed-off-by: Pierre-Louis Bossart Signed-off-by: Bard Liao Link: https://lore.kernel.org/r/20240429004321.2399754-5-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul

soundwire: intel_ace2.x: add support for DODSE property

2024-05-04T12:56:50+00:00

Extend previous patches with the DODSE field and property. Signed-off-by: Pierre-Louis Bossart Signed-off-by: Bard Liao Link: https://lore.kernel.org/r/20240429004321.2399754-4-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul

soundwire: intel_ace2x: use DOAIS and DODS settings from firmware

2024-05-04T12:56:50+00:00

Starting with LNL, the recommendation is to use settings read from DSD properties instead of hard-coding the values. The DOAIS and DODS values are completely-specific to Intel and are stored in a vendor-specific property structure. Signed-off-by: Pierre-Louis Bossart Signed-off-by: Bard Liao Link: https://lore.kernel.org/r/20240429004321.2399754-3-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul

soundwire: intel_ace2x: add debugfs support

2023-05-27T10:36:45+00:00

Add access to registers in SHIM and SHIM_VS (vendor-specific) areas. Signed-off-by: Pierre-Louis Bossart Reviewed-by: Rander Wang Reviewed-by: Péter Ujfalusi Reviewed-by: Ranjani Sridharan Signed-off-by: Bard Liao Link: https://lore.kernel.org/r/20230515071042.2038-11-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul