kernel/linux.git/drivers/soc/xilinx, branch v5.15.7

clk: xilinx: move xlnx_vcu clock driver from soc

2021-02-09T02:31:25+00:00

The xlnx_vcu driver is actually a clock controller driver which provides clocks that can be used by a driver for the encoder/decoder units. There is no reason to keep this driver in soc. Move the driver to clk. NOTE: The register mapping actually contains registers for AXI performance monitoring, but these are not used by the driver. Signed-off-by: Michael Tretter Acked-by: Michal Simek Link: https://lore.kernel.org/r/20210121071659.1226489-16-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd

soc: xilinx: vcu: fix alignment to open parenthesis

2021-02-09T02:31:25+00:00

Fixes the following checkpatch check: CHECK: Alignment should match open parenthesis #610: FILE: drivers/soc/xilinx/xlnx_vcu.c:610: + xvcu->vcu_slcr_ba = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); Signed-off-by: Michael Tretter Acked-by: Michal Simek Link: https://lore.kernel.org/r/20210121071659.1226489-15-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd

soc: xilinx: vcu: fix repeated word the in comment

2021-02-09T02:31:25+00:00

Fixes the following checkpatch warning: WARNING: Possible repeated word: 'the' #703: FILE: drivers/soc/xilinx/xlnx_vcu.c:703: + /* Add the the Gasket isolation and put the VCU in reset. */ Signed-off-by: Michael Tretter Acked-by: Michal Simek Link: https://lore.kernel.org/r/20210121071659.1226489-14-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd

soc: xilinx: vcu: use bitfields for register definition

2021-02-09T02:31:25+00:00

This makes the register accesses more readable and is closer to what is usually used in the kernel. Signed-off-by: Michael Tretter Reviewed-by: Stephen Boyd Acked-by: Michal Simek Link: https://lore.kernel.org/r/20210121071659.1226489-13-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd

soc: xilinx: vcu: remove calculation of PLL configuration

2021-02-09T02:31:25+00:00

As the consumers are now responsible for setting the clock rate via clock framework, the clock rate is now calculated using round_rate and the driver does not need to calculate the clock rate beforehand. Remove the code that calculates the PLL configuration. Signed-off-by: Michael Tretter Acked-by: Michal Simek Link: https://lore.kernel.org/r/20210121071659.1226489-12-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd

soc: xilinx: vcu: make the PLL configurable

2021-02-09T02:31:25+00:00

Do not configure the PLL when probing the driver, but register the clock in the clock framework and do the configuration based on the respective callbacks. This is necessary to allow the consumers, i.e., encoder and decoder drivers, of the xlnx_vcu clock provider to set the clock rate and actually enable the clocks without relying on some pre-configuration. Signed-off-by: Michael Tretter Acked-by: Michal Simek Link: https://lore.kernel.org/r/20210121071659.1226489-11-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd

soc: xilinx: vcu: make pll post divider explicit

2021-02-09T02:31:25+00:00

According to the downstream driver documentation due to timing constraints the output divider of the PLL has to be set to 1/2. Add a helper function for that check instead of burying the code in one large setup function. The bit is undocumented and marked as reserved in the register reference. Signed-off-by: Michael Tretter Acked-by: Michal Simek Link: https://lore.kernel.org/r/20210121071659.1226489-10-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd

soc: xilinx: vcu: implement clock provider for output clocks

2021-02-09T02:31:25+00:00

The VCU System-Level Control uses an internal PLL to drive the core and MCU clock for the allegro encoder and decoder based on an external PL clock. In order be able to ensure that the clocks are enabled and to get their rate from other drivers, the module must implement a clock provider and register the clocks at the common clock framework. Other drivers are then able to access the clock via devicetree bindings. Signed-off-by: Michael Tretter Acked-by: Michal Simek Link: https://lore.kernel.org/r/20210121071659.1226489-9-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd

soc: xilinx: vcu: register PLL as fixed rate clock

2021-02-09T02:31:25+00:00

Currently, xvcu_pll_set_rate configures the PLL to a clock rate that is pre-calculated when probing the driver. To still make the clock framework aware of the PLL and to allow to configure other clocks based on the PLL rate, register the PLL as a fixed rate clock. Signed-off-by: Michael Tretter Acked-by: Michal Simek Link: https://lore.kernel.org/r/20210121071659.1226489-8-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd

soc: xilinx: vcu: implement PLL disable

2021-02-09T02:31:25+00:00

The disabling of the PLL is not fully implemented, because according to the ZynqMP register reference the RESET, POR_IN and PWR_POR bits have to be set to bring the PLL into reset. Set the bits to disable the PLL. Signed-off-by: Michael Tretter Acked-by: Michal Simek Link: https://lore.kernel.org/r/20210121071659.1226489-7-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd