<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/soc/xilinx/Makefile, branch linux-4.16.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.16.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.16.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2018-01-08T12:42:47+00:00</updated>
<entry>
<title>soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver</title>
<updated>2018-01-08T12:42:47+00:00</updated>
<author>
<name>Dhaval Shah</name>
<email>dhaval.shah@xilinx.com</email>
</author>
<published>2017-12-21T18:33:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=cee8113a295acfc4cd25728d7c3d44e6bc3bbff9'/>
<id>urn:sha1:cee8113a295acfc4cd25728d7c3d44e6bc3bbff9</id>
<content type='text'>
Xilinx ZYNQMP logicoreIP Init driver is based on the new
LogiCoreIP design created. This driver provides the processing system
and programmable logic isolation. Set the frequency based on the clock
information get from the logicoreIP register set.

Signed-off-by: Dhaval Shah &lt;dshah@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>soc: xilinx: Create folder structure for soc specific drivers</title>
<updated>2018-01-08T12:42:39+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2017-12-19T13:15:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5abcdc206fe8383f1e74d6cbce2f16ff0b121715'/>
<id>urn:sha1:5abcdc206fe8383f1e74d6cbce2f16ff0b121715</id>
<content type='text'>
Create directory structure with Makefile/Kconfig for adding xilinx soc
specific drivers.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
</feed>
