<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/soc/tegra, branch v4.17.1</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v4.17.1</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v4.17.1'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2018-03-19T08:42:39+00:00</updated>
<entry>
<title>soc/tegra: pmc: Use the new reset APIs to manage reset controllers</title>
<updated>2018-03-19T08:42:39+00:00</updated>
<author>
<name>Vivek Gautam</name>
<email>vivek.gautam@codeaurora.org</email>
</author>
<published>2017-07-19T15:59:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4c817ccf73abaf7b06a2630e8352d82648c8bc70'/>
<id>urn:sha1:4c817ccf73abaf7b06a2630e8352d82648c8bc70</id>
<content type='text'>
Make use of of_reset_control_array_get_exclusive() to manage
an array of reset controllers available with the device.

Cc: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Cc: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Vivek Gautam &lt;vivek.gautam@codeaurora.org&gt;
[p.zabel@pengutronix.de: switch to hidden reset control array]
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Pass PMC to tegra_powergate_power_up()</title>
<updated>2018-03-08T16:02:43+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-02-12T15:09:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=507c655a06c8553a67122c371608b024b997b0e0'/>
<id>urn:sha1:507c655a06c8553a67122c371608b024b997b0e0</id>
<content type='text'>
tegra_powergate_sequence_power_up() makes up a struct tegra_powergate
from scratch in order to reuse the same code as used by the generic PM
domain implementation. However, subsequent patches will need to access
the struct tegra_pmc * embedded in the powergate structure, so we need
to make sure we always pass it in.

Tested-by: Hector Martin &lt;marcan@marcan.st&gt;
Tested-by: Andre Heider &lt;a.heider@gmail.com&gt;
Tested-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: MBIST work around for Tegra210</title>
<updated>2018-03-08T16:02:24+00:00</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2018-01-25T14:00:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a263394a096e3578eb8dd77039b961c84a7392e7'/>
<id>urn:sha1:a263394a096e3578eb8dd77039b961c84a7392e7</id>
<content type='text'>
Apply the memory built-in self test work around when ungating certain
Tegra210 power domains.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Hector Martin &lt;marcan@marcan.st&gt;
Tested-by: Andre Heider &lt;a.heider@gmail.com&gt;
Tested-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Add Tegra194 compatibility string</title>
<updated>2018-03-08T15:44:01+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2018-02-20T11:58:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=56327f54d95c05791fd01e59a9dc03e3a4eafd21'/>
<id>urn:sha1:56327f54d95c05791fd01e59a9dc03e3a4eafd21</id>
<content type='text'>
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Add Tegra194 SoC configuration option</title>
<updated>2018-03-08T15:44:01+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2018-02-20T11:58:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6f9ed07fde03870ec247dcaf244313fe32521545'/>
<id>urn:sha1:6f9ed07fde03870ec247dcaf244313fe32521545</id>
<content type='text'>
Add the configuration option to enable support for the Tegra194 system-
on-chip.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Explicitly request DMA channel from APB DMA driver</title>
<updated>2017-12-21T16:04:12+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2017-10-19T22:08:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ccf151847b81a3ad779b64f5f71f0632f2009eb6'/>
<id>urn:sha1:ccf151847b81a3ad779b64f5f71f0632f2009eb6</id>
<content type='text'>
Currently fuse driver requests DMA channel from an arbitrary DMA device,
it is not a problem since there is only one DMA provider for Tegra20 yet,
but it may become troublesome if another provider will appear.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Fix reading registers using DMA on Tegra20</title>
<updated>2017-12-21T16:03:49+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2017-10-19T22:08:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=55a042b3f68fc8c68adf4333ff74c4d3de796589'/>
<id>urn:sha1:55a042b3f68fc8c68adf4333ff74c4d3de796589</id>
<content type='text'>
FUSE driver doesn't configure DMA channel properly, because of it DMA
transfer is never issued and tegra20_fuse_read() always return 0x0.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Consolidate Tegra186 support</title>
<updated>2017-12-13T12:06:44+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-08-30T10:42:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c641ec6eab8587a78160d37f085a5ed6e542ca88'/>
<id>urn:sha1:c641ec6eab8587a78160d37f085a5ed6e542ca88</id>
<content type='text'>
Move Tegra186 support to the consolidated PMC driver to reduce some of
the duplication and also gain I/O pad functionality on the new SoC as a
side-effect.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Parameterize driver</title>
<updated>2017-12-13T12:04:50+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-08-30T10:32:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5be2255676bf2bc69170f05cfe15f771e5aeef24'/>
<id>urn:sha1:5be2255676bf2bc69170f05cfe15f771e5aeef24</id>
<content type='text'>
Parameterize some aspects of the driver in preparation for Tegra186 PMC
support. Initially the Tegra186 driver had been split off into an extra
driver, but it turns out the backwards-compatibility break isn't as bad
as originally assumed, so with a little parameterization the same code
can be used to keep supporting all SoC generations.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Add Tegra186 chip ID support</title>
<updated>2017-12-13T11:43:31+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-06-26T15:25:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=75c15b90e42373a3c651d53e6e55239b0f03777d'/>
<id>urn:sha1:75c15b90e42373a3c651d53e6e55239b0f03777d</id>
<content type='text'>
The register region containing chip ID information has been relocated in
Tegra186 and changed in backwards-incompatible ways. Add a compatible
string to allow the driver to make the distinction.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
