kernel/linux.git/drivers/soc/tegra/fuse, branch linux-5.9.y

soc/tegra: fuse: Fix typo in APB MISC warning

2020-07-17T13:47:35+00:00

The hardware block is called APB MISC, not ABP MISC, so fix the warning to use the correct name. Signed-off-by: Thierry Reding

soc/tegra: fuse: Update the SoC revision attribute to display a name

2020-04-21T22:08:05+00:00

Currently the SoC revision attribute for Tegra devices displays the value of the enum associated with a particular revision. This is not very useful because to obtain the actual revision you need to use the tegra_revision enumeration to translate the value. It is more meaningful to display a name for the revision, such as 'A01', than the enumarated value and therefore, update the revision attribute to display a name. This change does alter the ABI, which is unfortunate, but this is more meaningful and maintable. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding

soc/tegra: fuse: Trivial clean-up of tegra_init_revision()

2020-04-21T22:07:27+00:00

Clean-up the tegra_init_revision() function by removing the 'rev' variable which is not needed and use the newly added helper function tegra_get_minor_rev() to get the minor revision. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding

soc/tegra: fuse: Add custom SoC attributes

2020-04-21T22:07:23+00:00

Add a custom SoC attribute for Tegra to expose the HIDREV register fields to userspace via the sysfs. This register provides additional details about the type of device (eg, silicon, FPGA, etc) as well as revision. Exposing this information is useful for identifying the exact device revision and device type. For Tegra devices up until Tegra186, the majorrev and minorrev fields of the HIDREV register are used to determine the device revision and device type. For Tegra194, the majorrev and minorrev fields only determine the revision. Starting with Tegra194, there is an additional field, pre_si_platform (which occupies bits 20-23), that now determines device type. Therefore, for all Tegra devices, add a custom SoC attribute for the majorrev and minorrev fields and for Tegra194 add an additional attribute for the pre_si_platform field. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding

soc/tegra: fuse: Fix build with Tegra194 configuration

2020-02-11T23:00:15+00:00

If only Tegra194 support is enabled, the tegra30_fuse_read() and tegra30_fuse_init() function are not declared and cause a build failure. Add Tegra194 to the preprocessor guard to make sure these functions are available for Tegra194-only builds as well. Link: https://lore.kernel.org/r/20200203143114.3967295-1-thierry.reding@gmail.com Reported-by: kbuild test robot Signed-off-by: Thierry Reding Signed-off-by: Olof Johansson

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2020-02-08T22:04:19+00:00

Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms: - Nvidia: Fuse support for Tegra194, continued memory controller pieces for Tegra30 - NXP/FSL: Refactorings of QuickEngine drivers to support ARM/ARM64/PPC - NXP/FSL: i.MX8MP SoC driver pieces - TI Keystone: ring accelerator driver - Qualcomm: SCM driver cleanup/refactoring + support for new SoCs. - Xilinx ZynqMP: feature checking interface for firmware. Mailbox communication for power management - Overall support patch set for cpuidle on more complex hierarchies (PSCI-based) and misc cleanups, refactorings of Marvell, TI, other platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (166 commits) drivers: soc: xilinx: Use mailbox IPI callback dt-bindings: power: reset: xilinx: Add bindings for ipi mailbox drivers: soc: ti: knav_qmss_queue: Pass lockdep expression to RCU lists MAINTAINERS: Add brcmstb PCIe controller entry soc/tegra: fuse: Unmap registers once they are not needed anymore soc/tegra: fuse: Correct straps' address for older Tegra124 device trees soc/tegra: fuse: Warn if straps are not ready soc/tegra: fuse: Cache values of straps and Chip ID registers memory: tegra30-emc: Correct error message for timed out auto calibration memory: tegra30-emc: Firm up hardware programming sequence memory: tegra30-emc: Firm up suspend/resume sequence soc/tegra: regulators: Do nothing if voltage is unchanged memory: tegra: Correct reset value of xusb_hostr soc/tegra: fuse: Add APB DMA dependency for Tegra20 bus: tegra-aconnect: Remove PM_CLK dependency dt-bindings: mediatek: add MT6765 power dt-bindings soc: mediatek: cmdq: delete not used define memory: tegra: Add support for the Tegra194 memory controller memory: tegra: Only include support for enabled SoCs memory: tegra: Support DVFS on Tegra186 and later ...

soc/tegra: fuse: Unmap registers once they are not needed anymore

2020-01-10T14:59:43+00:00

Both Chip ID and strapping registers are now read out during of APB MISC initialization, the registers' mapping isn't needed anymore once registers are read. Hence let's unmap registers once they are not needed anymore, for consistency. Suggested-by: Michał Mirosław Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

soc/tegra: fuse: Correct straps' address for older Tegra124 device trees

2020-01-10T14:59:01+00:00

Trying to read out Chip ID before APBMISC registers are mapped won't succeed, in a result Tegra124 gets a wrong address for the HW straps register if machine uses an old outdated device tree. Fixes: 297c4f3dcbff ("soc/tegra: fuse: Restrict legacy code to 32-bit ARM") Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

soc/tegra: fuse: Warn if straps are not ready

2020-01-10T14:58:48+00:00

Now both Chip ID and HW straps are becoming available at the same time, thus we could simply check the availability of the ID in order to check the availability of the straps. We couldn't check straps for 0x0 because it could be a correct value. This change didn't uncover any problems, but anyways it is nicer to have straps verified for consistency with the Chip ID verification. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

soc/tegra: fuse: Cache values of straps and Chip ID registers

2020-01-10T14:58:32+00:00

There is no need to re-read Chip ID and HW straps out from hardware each time, it is a bit nicer to cache the values in memory. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding