Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.4.y 2021-12-22T08:04:18+00:00 2021-12-22T08:04:18+00:00 Nathan Chancellor nathan@kernel.org 2021-12-10T16:55:29+00:00 urn:sha1:22feeef263c5f8c3ac2602ff5a00df7db56c7f01 [ Upstream commit a7083763619f7485ccdade160deb81737cf2732f ] A new warning in clang points out two instances where boolean expressions are being used with a bitwise OR instead of logical OR: drivers/soc/tegra/fuse/speedo-tegra20.c:72:9: warning: use of bitwise '|' with boolean operands [-Wbitwise-instead-of-logical] reg = tegra_fuse_read_spare(i) | ^~~~~~~~~~~~~~~~~~~~~~~~~~ || drivers/soc/tegra/fuse/speedo-tegra20.c:72:9: note: cast one or both operands to int to silence this warning drivers/soc/tegra/fuse/speedo-tegra20.c:87:9: warning: use of bitwise '|' with boolean operands [-Wbitwise-instead-of-logical] reg = tegra_fuse_read_spare(i) | ^~~~~~~~~~~~~~~~~~~~~~~~~~ || drivers/soc/tegra/fuse/speedo-tegra20.c:87:9: note: cast one or both operands to int to silence this warning 2 warnings generated. The motivation for the warning is that logical operations short circuit while bitwise operations do not. In this instance, tegra_fuse_read_spare() is not semantically returning a boolean, it is returning a bit value. Use u32 for its return type so that it can be used with either bitwise or boolean operators without any warnings. Fixes: 25cd5a391478 ("ARM: tegra: Add speedo-based process identification") Link: https://github.com/ClangBuiltLinux/linux/issues/1488 Suggested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org> 2020-12-29T12:42:34+00:00 Nicolin Chen nicoleotsuka@gmail.com 2020-11-19T04:44:57+00:00 urn:sha1:47bd0654d29d3631bd7ab7eeffe5ec91ca4c51a2 commit b9ce9b0f83b536a4ac7de7567a265d28d13e5bea upstream. This patch simply fixes a bug of referencing speedos[num] in every for-loop iteration in get_process_id function. Fixes: 0dc5a0d83675 ("soc/tegra: fuse: Add Tegra210 support") Cc: <stable@vger.kernel.org> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2020-02-28T14:39:02+00:00 Dmitry Osipenko digetx@gmail.com 2019-12-18T18:23:03+00:00 urn:sha1:45821bd9bffab58422cf91c795b96ce80b43fd97 [ Upstream commit 2d9ea1934f8ef0dfb862d103389562cc28b4fc03 ] Trying to read out Chip ID before APBMISC registers are mapped won't succeed, in a result Tegra124 gets a wrong address for the HW straps register if machine uses an old outdated device tree. Fixes: 297c4f3dcbff ("soc/tegra: fuse: Restrict legacy code to 32-bit ARM") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org> 2019-04-27T07:33:52+00:00 Timo Alho talho@nvidia.com 2018-12-30T15:58:08+00:00 urn:sha1:cdc7a66f679e5fb1f60a41a3766e1cbe309d3e82 [ Upstream commit 51294bf6b9e897d595466dcda5a3f2751906a200 ] On cases where device tree entries for fuse and clock provider are in different order, fuse driver needs to defer probing. This leads to freeing incorrect IO base address as the fuse->base variable gets overwritten once during first probe invocation. This leads to the following spew during boot: [ 3.082285] Trying to vfree() nonexistent vm area (00000000cfe8fd94) [ 3.082308] WARNING: CPU: 5 PID: 126 at /hdd/l4t/kernel/stable/mm/vmalloc.c:1511 __vunmap+0xcc/0xd8 [ 3.082318] Modules linked in: [ 3.082330] CPU: 5 PID: 126 Comm: kworker/5:1 Tainted: G S 4.19.7-tegra-gce119d3 #1 [ 3.082340] Hardware name: quill (DT) [ 3.082353] Workqueue: events deferred_probe_work_func [ 3.082364] pstate: 40000005 (nZcv daif -PAN -UAO) [ 3.082372] pc : __vunmap+0xcc/0xd8 [ 3.082379] lr : __vunmap+0xcc/0xd8 [ 3.082385] sp : ffff00000a1d3b60 [ 3.082391] x29: ffff00000a1d3b60 x28: 0000000000000000 [ 3.082402] x27: 0000000000000000 x26: ffff000008e8b610 [ 3.082413] x25: 0000000000000000 x24: 0000000000000009 [ 3.082423] x23: ffff000009221a90 x22: ffff000009f6d000 [ 3.082432] x21: 0000000000000000 x20: 0000000000000000 [ 3.082442] x19: ffff000009f6d000 x18: ffffffffffffffff [ 3.082452] x17: 0000000000000000 x16: 0000000000000000 [ 3.082462] x15: ffff0000091396c8 x14: 0720072007200720 [ 3.082471] x13: 0720072007200720 x12: 0720072907340739 [ 3.082481] x11: 0764076607380765 x10: 0766076307300730 [ 3.082491] x9 : 0730073007300730 x8 : 0730073007280720 [ 3.082501] x7 : 0761076507720761 x6 : 0000000000000102 [ 3.082510] x5 : 0000000000000000 x4 : 0000000000000000 [ 3.082519] x3 : ffffffffffffffff x2 : ffff000009150ff8 [ 3.082528] x1 : 3d95b1429fff5200 x0 : 0000000000000000 [ 3.082538] Call trace: [ 3.082545] __vunmap+0xcc/0xd8 [ 3.082552] vunmap+0x24/0x30 [ 3.082561] __iounmap+0x2c/0x38 [ 3.082569] tegra_fuse_probe+0xc8/0x118 [ 3.082577] platform_drv_probe+0x50/0xa0 [ 3.082585] really_probe+0x1b0/0x288 [ 3.082593] driver_probe_device+0x58/0x100 [ 3.082601] __device_attach_driver+0x98/0xf0 [ 3.082609] bus_for_each_drv+0x64/0xc8 [ 3.082616] __device_attach+0xd8/0x130 [ 3.082624] device_initial_probe+0x10/0x18 [ 3.082631] bus_probe_device+0x90/0x98 [ 3.082638] deferred_probe_work_func+0x74/0xb0 [ 3.082649] process_one_work+0x1e0/0x318 [ 3.082656] worker_thread+0x228/0x450 [ 3.082664] kthread+0x128/0x130 [ 3.082672] ret_from_fork+0x10/0x18 [ 3.082678] ---[ end trace 0810fe6ba772c1c7 ]--- Fix this by retaining the value of fuse->base until driver has successfully probed. Signed-off-by: Timo Alho <talho@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org> 2015-07-16T08:38:31+00:00 Thierry Reding treding@nvidia.com 2015-05-04T14:45:25+00:00 urn:sha1:1dad36cdd5d20b4d7ceca5026553e86b3315b022 The offset of the first spare bit register on Tegra210 is 0x380, but account for the fixed offset of 0x100 in the fuse accessor. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-07-16T08:38:31+00:00 Thierry Reding treding@nvidia.com 2015-05-04T14:44:29+00:00 urn:sha1:82df0e5e78d956ea3552f7315a4d559f657047da The offset of the first spare bit register on Tegra124 is 0x300, but account for the fixed offset of 0x100 in the fuse accessor. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-07-16T08:38:30+00:00 Thierry Reding treding@nvidia.com 2015-05-04T14:38:28+00:00 urn:sha1:b23083a9c6829675d367b4f06a64d74ead82eb14 The offset of the first spare bit register on Tegra114 is 0x280, but account for the fixed offset of 0x100 in the fuse accessor. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-07-16T08:38:29+00:00 Thierry Reding treding@nvidia.com 2015-03-23T13:44:08+00:00 urn:sha1:03b3f4c8b76180ba5bd800c57a7efdb142c2341d There's a mixture of core_* and soc_* prefixes for variables storing information related to the VDD_CORE rail. Choose one (soc_*) and use it more consistently. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-07-16T08:38:29+00:00 Thierry Reding treding@nvidia.com 2015-04-29T14:55:57+00:00 urn:sha1:0dc5a0d836751099f2e08deec28f56ec881925dd Add Tegra210 support to the fuses driver and add Tegra210-specific speedo definitions. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-07-16T08:38:28+00:00 Thierry Reding treding@nvidia.com 2015-04-29T14:54:04+00:00 urn:sha1:7e939de1b2bb26496e4967e5346619700245e7c0 Unifying the drivers makes it easier to restrict the legacy probing paths to 32-bit ARM. This in turn will come in handy as support for new 64-bit ARM SoCs is added. Signed-off-by: Thierry Reding <treding@nvidia.com>