kernel/linux.git/drivers/soc/tegra/Kconfig, branch v6.3

Merge tag 'soc-fixes-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2022-12-19T22:07:59+00:00

Pull ARM SoC fixes from Arnd Bergmann: "These are a couple of build fixes from randconfig testing, plus a set of Mediatek SoC specific fixes, all trivial" * tag 'soc-fixes-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: soc: tegra: fix CPU_BIG_ENDIAN dependencies ARM: disallow pre-ARMv5 builds with ld.lld ARM: pxa: fix building with clang MAINTAINERS: add related dts to IXP4xx ARM: dts: spear: drop 0x from unit address arm64: dts: mt8183: Fix Mali GPU clock arm64: dts: mediatek: mt8195-demo: fix the memory size of node secmon soc: mediatek: pm-domains: Fix the power glitch issue

soc: tegra: fix CPU_BIG_ENDIAN dependencies

2022-12-19T15:47:01+00:00

My previous patch to prevent BPMP from being enabled on big endian kernels caused a build regression: WARNING: unmet direct dependencies detected for TEGRA_BPMP Depends on [n]: ARCH_TEGRA [=y] && TEGRA_HSP_MBOX [=y] && TEGRA_IVC [=y] && !CPU_BIG_ENDIAN [=y] Selected by [y]: - ARCH_TEGRA_186_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] - ARCH_TEGRA_194_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] - ARCH_TEGRA_234_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] Add even more such dependencies for the SoC types that use the BPMP driver. Fixes: 4ddb1bf1a837 ("tegra: mark BPMP driver as little-endian only") Signed-off-by: Arnd Bergmann Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20221215165336.1781080-1-arnd@kernel.org Signed-off-by: Arnd Bergmann

soc/tegra: pmc: Select IRQ_DOMAIN_HIERARCHY

2022-10-24T15:05:51+00:00

Tegra PMC driver depends on IRQ domain hierarchy support, hence select the IRQ_DOMAIN_HIERARCHY config for SOC_TEGRA_PMC. Signed-off-by: Petlozu Pravareshwar Signed-off-by: Thierry Reding

Merge tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

2022-09-23T16:04:29+00:00

soc/tegra: cbb: Changes for v6.1-rc1 This introduces the CBB driver that is used to provide (a lot of) information about SErrors when things go wrong, instead of the kernel just crashing or hanging. * tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: cbb: Add support for Tegra241 (Grace) soc/tegra: cbb: Add driver for Tegra234 CBB 2.0 soc/tegra: cbb: Add CBB 1.0 driver for Tegra194 soc/tegra: Set ERD bit to mask inband errors Link: https://lore.kernel.org/r/20220916101957.1635854-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann

soc/tegra: fuse: Drop Kconfig dependency on TEGRA20_APB_DMA

2022-09-15T10:49:14+00:00

The DMA subsystem could be entirely disabled in Kconfig and then the TEGRA20_APB_DMA option isn't available too. Hence kernel configuration fails if DMADEVICES Kconfig option is disabled due to the unsatisfiable dependency. The FUSE driver isn't a critical driver and currently it only provides NVMEM interface to userspace which isn't known to be widely used, and thus, it's fine if FUSE driver fails to load. Let's remove the erroneous Kconfig dependency and let the FUSE driver to fail the probing if DMA is unavailable. Fixes: 19d41e5e9c68 ("soc/tegra: fuse: Add APB DMA dependency for Tegra20") Reported-by: Necip Fazil Yildiran Link: https://bugzilla.kernel.org/show_bug.cgi?id=209301 Signed-off-by: Dmitry Osipenko

soc/tegra: cbb: Add driver for Tegra234 CBB 2.0

2022-09-15T10:41:36+00:00

Adding driver to handle errors from CBB version 2.0 which is used in Tegra234 SoC. The driver prints debug information about failed transaction on receiving interrupt from the error notifier. The error notifier collates the interrupts from various error monitor blocks and presents a single interrupt to the SoC interrupt controller. For timeout errors, the driver also does the lookup to find timed out clients and prints their client ID. Drivers for hardware that needs to be reset on timeout will have to call BPMP from the client IP's driver. BPMP firmware will also clear the timeout bit after resetting the IP so that next transactions are send to them after reset. Signed-off-by: Sumit Gupta Signed-off-by: Thierry Reding

soc/tegra: cbb: Add CBB 1.0 driver for Tegra194

2022-09-15T10:41:36+00:00

Adding driver to handle errors from Control Backbone (CBB) which are generated due to illegal accesses. CBB 1.0 is used in Tegra194 SoCs. When an error is reported from a NOC within CBB, the driver prints debug information about failed transaction like Error Code, Error Description, Master, Address, AXI ID, Cache, Protection, Security Group etc. It then causes system crash using BUG_ON() or call WARN() based on whether the error type is fatal or not. Signed-off-by: Sumit Gupta Signed-off-by: Thierry Reding

soc/tegra: pmc: Select REGMAP

2022-05-04T09:09:49+00:00

Commit 9d5e7c3e36eb ("soc/tegra: pmc: Provide USB sleepwalk register map") introduced a dependency on the regmap infrastructure, so select the corresponding Kconfig entry. This avoids failures in random builds that may otherwise end up having SOC_TEGRA_PMC enabled but not REGMAP. Signed-off-by: Thierry Reding

soc/tegra: Make regulator couplers depend on CONFIG_REGULATOR

2021-08-02T12:30:46+00:00

The regulator coupler drivers now use regulator-driver API function that isn't available during compile-testing. Make regulator coupler drivers dependent on CONFIG_REGULATOR in Kconfig. Fixes: 03978d42ed0d ("soc/tegra: regulators: Bump voltages on system reboot") Reported-by: kernel test robot Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Signed-off-by: Arnd Bergmann

soc/tegra: pmc: Add core power domain

2021-06-02T08:58:42+00:00

NVIDIA Tegra SoCs have multiple power domains, each domain corresponds to an external SoC power rail. Core power domain covers vast majority of hardware blocks within a Tegra SoC. The voltage of a power domain should be set to a level which satisfies all devices within the power domain. Add support for the core power domain which controls voltage state of the domain. This allows us to support system-wide DVFS on Tegra20-210 SoCs. The PMC powergate domains now are sub-domains of the core domain, this requires device-tree updating, older DTBs are unaffected and will continue to work as before. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko Reviewed-by: Ulf Hansson [treding@nvidia.com: squash lockdep class removal patch] Signed-off-by: Thierry Reding