<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/soc/sifive, branch v6.1.168</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2022-12-31T12:31:50+00:00</updated>
<entry>
<title>soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()</title>
<updated>2022-12-31T12:31:50+00:00</updated>
<author>
<name>Yang Yingliang</name>
<email>yangyingliang@huawei.com</email>
</author>
<published>2022-10-18T02:31:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5e1a9c98c116a5d2a43d5412dcb20d92783afa48'/>
<id>urn:sha1:5e1a9c98c116a5d2a43d5412dcb20d92783afa48</id>
<content type='text'>
[ Upstream commit 8fbf94fea0b4e187ca9100936c5429f96b8a4e44 ]

The device_node pointer returned by of_find_matching_node() with
refcount incremented, when finish using it, the refcount need be
decreased.

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang &lt;yangyingliang@huawei.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()</title>
<updated>2022-12-31T12:31:50+00:00</updated>
<author>
<name>Yang Yingliang</name>
<email>yangyingliang@huawei.com</email>
</author>
<published>2022-10-18T02:31:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0883dc428c95c123228a4acf340ff21ce5bdd8a3'/>
<id>urn:sha1:0883dc428c95c123228a4acf340ff21ce5bdd8a3</id>
<content type='text'>
[ Upstream commit 756344e7cb1afbb87da8705c20384dddd0dea233 ]

Add missing free_irq() before return error from sifive_ccache_init().

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang &lt;yangyingliang@huawei.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()</title>
<updated>2022-12-31T12:31:50+00:00</updated>
<author>
<name>Yang Yingliang</name>
<email>yangyingliang@huawei.com</email>
</author>
<published>2022-10-18T02:31:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7ea9128d1a91001edd954dd1b8cf5666145ddafe'/>
<id>urn:sha1:7ea9128d1a91001edd954dd1b8cf5666145ddafe</id>
<content type='text'>
[ Upstream commit 73e770f085023da327dc9ffeb6cd96b0bb22d97e ]

Add missing iounmap() before return error from sifive_ccache_init().

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang &lt;yangyingliang@huawei.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: define the macro for the register shifts</title>
<updated>2022-10-13T18:06:55+00:00</updated>
<author>
<name>Zong Li</name>
<email>zong.li@sifive.com</email>
</author>
<published>2022-09-13T06:18:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=afc7a5834f0de13aee46df62f09e479c1bbf7b9d'/>
<id>urn:sha1:afc7a5834f0de13aee46df62f09e479c1bbf7b9d</id>
<content type='text'>
Define the macro for the register shifts, it could make the code be
more readable

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes</title>
<updated>2022-10-13T18:06:54+00:00</updated>
<author>
<name>Ben Dooks</name>
<email>ben.dooks@sifive.com</email>
</author>
<published>2022-09-13T06:18:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=696ab9bda22a770d079dc3a23bac9aaa553d98f4'/>
<id>urn:sha1:696ab9bda22a770d079dc3a23bac9aaa553d98f4</id>
<content type='text'>
Use the pr_fmt() macro to prefix all the output with "CCACHE:"
to avoid having to write it out each time, or make a large diff
when the next change comes along.

Signed-off-by: Ben Dooks &lt;ben.dooks@sifive.com&gt;
Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: reduce printing on init</title>
<updated>2022-10-13T18:06:53+00:00</updated>
<author>
<name>Ben Dooks</name>
<email>ben.dooks@sifive.com</email>
</author>
<published>2022-09-13T06:18:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3fb787e5bad50687a65ded7f3bb805cab70dff59'/>
<id>urn:sha1:3fb787e5bad50687a65ded7f3bb805cab70dff59</id>
<content type='text'>
The driver prints out 6 lines on startup, which can easily be redcued
to two lines without losing any information.

Note, to make the types work better, uint64_t has been replaced with
ULL to make the unsigned long long match the format in the print
statement.

Signed-off-by: Ben Dooks &lt;ben.dooks@sifive.com&gt;
Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-5-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: determine the cache level from dts</title>
<updated>2022-10-13T18:06:52+00:00</updated>
<author>
<name>Zong Li</name>
<email>zong.li@sifive.com</email>
</author>
<published>2022-09-13T06:18:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=95f196f3212bbc258611c22865aef12b98304e1d'/>
<id>urn:sha1:95f196f3212bbc258611c22865aef12b98304e1d</id>
<content type='text'>
Composable cache could be L2 or L3 cache, use 'cache-level' property of
device node to determine the level.

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.</title>
<updated>2022-10-13T18:06:51+00:00</updated>
<author>
<name>Greentime Hu</name>
<email>greentime.hu@sifive.com</email>
</author>
<published>2022-09-13T06:18:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ca120a79cf5a3323172c82e77efd70ae10d120ef'/>
<id>urn:sha1:ca120a79cf5a3323172c82e77efd70ae10d120ef</id>
<content type='text'>
Since composable cache may be L3 cache if there is a L2 cache, we should
use its original name composable cache to prevent confusion.

There are some new lines were generated due to adding the compatible
"sifive,ccache0" into ID table and indent requirement.

The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to
apply the change as well.

Signed-off-by: Greentime Hu &lt;greentime.hu@sifive.com&gt;
Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Co-developed-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740</title>
<updated>2021-01-08T01:28:27+00:00</updated>
<author>
<name>Yash Shah</name>
<email>yash.shah@sifive.com</email>
</author>
<published>2020-12-10T10:28:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=507308b8ccc90d37b07bfca8ffe130435d6b354f'/>
<id>urn:sha1:507308b8ccc90d37b07bfca8ffe130435d6b354f</id>
<content type='text'>
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.

Signed-off-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>soc: sifive: l2 cache: Mark l2_get_priv_group as static</title>
<updated>2020-05-28T22:57:49+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmerdabbelt@google.com</email>
</author>
<published>2020-05-28T22:39:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=09c0533d129ce460e6214c14f744ddbac3733889'/>
<id>urn:sha1:09c0533d129ce460e6214c14f744ddbac3733889</id>
<content type='text'>
The kbuild test robot is firing a warning over a missing prototype.  The
function can just be static.

Reported-by: kbuild test robot &lt;lkp@intel.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
</feed>
