kernel/linux.git/drivers/soc/sifive, branch linux-5.9.y

soc: sifive: l2 cache: Mark l2_get_priv_group as static

2020-05-28T22:57:49+00:00

The kbuild test robot is firing a warning over a missing prototype. The function can just be static. Reported-by: kbuild test robot Signed-off-by: Palmer Dabbelt

soc: sifive: l2 cache: Eliminate an unsigned zero compare warning

2020-05-28T22:57:48+00:00

GCC warns about this comparison, which is unnecessary. Signed-off-by: Palmer Dabbelt

riscv: Add support to determine no. of L2 cache way enabled

2020-05-20T22:05:10+00:00

In order to determine the number of L2 cache ways enabled at runtime, implement a private attribute ("number_of_ways_enabled"). Reading this attribute returns the number of enabled L2 cache ways at runtime. Using riscv_set_cacheinfo_ops() hook a custom function, that returns this private attribute, to the generic ops structure which is used by cache_get_priv_group() in cacheinfo framework. Signed-off-by: Yash Shah Reviewed-by: Anup Patel Signed-off-by: Palmer Dabbelt

riscv: move sifive_l2_cache.h to include/soc

2020-01-12T18:12:44+00:00

The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") moves the sifive L2 cache driver to driver/soc. It did not move the header file along with the driver. Therefore this patch moves the header file to driver/soc Signed-off-by: Yash Shah Reviewed-by: Anup Patel [paul.walmsley@sifive.com: updated to fix the include guard] Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") Signed-off-by: Paul Walmsley

riscv: move sifive_l2_cache.c to drivers/soc

2019-12-20T11:40:24+00:00

The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig Reviewed-by: Borislav Petkov [paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code] Signed-off-by: Paul Walmsley