kernel/linux.git/drivers/soc/rockchip, branch v4.14.286

soc: rockchip: Fix refcount leak in rockchip_grf_init

2022-06-14T14:53:56+00:00

[ Upstream commit 9b59588d8be91c96bfb0371e912ceb4f16315dbf ] of_find_matching_node_and_match returns a node pointer with refcount incremented, we should use of_node_put() on it when done. Add missing of_node_put() to avoid refcount leak. Fixes: 4c58063d4258 ("soc: rockchip: add driver handling grf setup") Signed-off-by: Miaoqian Lin Link: https://lore.kernel.org/r/20220516072013.19731-1-linmq006@gmail.com Signed-off-by: Heiko Stuebner Signed-off-by: Sasha Levin

soc: rockchip: ROCKCHIP_GRF should not default to y, unconditionally

2021-09-22T09:45:19+00:00

[ Upstream commit 2a1c55d4762dd34a8b0f2e36fb01b7b16b60735b ] Merely enabling CONFIG_COMPILE_TEST should not enable additional code. To fix this, restrict the automatic enabling of ROCKCHIP_GRF to ARCH_ROCKCHIP, and ask the user in case of compile-testing. Fixes: 4c58063d4258f6be ("soc: rockchip: add driver handling grf setup") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20210208143855.418374-1-geert+renesas@glider.be Signed-off-by: Heiko Stuebner Signed-off-by: Sasha Levin

soc: rockchip: Set the proper PWM for rk3288

2019-06-15T09:54:55+00:00

[ Upstream commit bbdc00a7de24cc90315b1775fb74841373fe12f7 ] The rk3288 SoC has two PWM implementations available, the "old" implementation and the "new" one. You can switch between the two of them by flipping a bit in the grf. The "old" implementation is the default at chip power up but isn't the one that's officially supposed to be used. ...and, in fact, the driver that gets selected in Linux using the rk3288 device tree only supports the "new" implementation. Long ago I tried to get a switch to the right IP block landed in the PWM driver (search for "rk3288: Switch to use the proper PWM IP") but that got rejected. In the mean time the grf has grown a full-fledged driver that already sets other random bits like this. That means we can now get the fix landed. For those wondering how things could have possibly worked for the last 4.5 years, folks have mostly been relying on the bootloader to set this bit. ...but occasionally folks have pointed back to my old patch series [1] in downstream kernels. [1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1391597.html Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner Signed-off-by: Sasha Levin

soc: rockchip: power-domain: Fix wrong value when power up pd with writemask

2018-07-03T09:24:51+00:00

commit 9e59c5f66c624b43c766a9fe3b2430e0e976bf0e upstream. Solve the pd could only ever turn off but never turn them on again, if the pd registers have the writemask bits. So far this affects the rk3328 only. Fixes: 79bb17ce8edb ("soc: rockchip: power-domain: Support domain control in hiword-registers") Cc: stable@vger.kernel.org Signed-off-by: Finley Xiao Signed-off-by: Elaine Zhang Reviewed-by: Ulf Hansson Signed-off-by: Heiko Stuebner Signed-off-by: Greg Kroah-Hartman

soc: rockchip: power-domain: add power domain support for rk3366

2017-07-20T20:42:19+00:00

This driver is modified to support RK3366 SoC. Signed-off-by: Elaine Zhang Signed-off-by: Heiko Stuebner

soc: rockchip: disable jtag switching for RK3328 Soc

2017-07-16T15:08:12+00:00

Disable IO function switching between sdmmc and jtag for RK3328 Soc. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner

soc: rockchip: add driver handling grf setup

2017-01-06T09:28:19+00:00

The General Register Files are an area of registers containing a lot of single-bit settings for numerous components as well full components like usbphy control. Therefore all used components are accessed via the syscon provided by the grf nodes or from the sub-devices created through the simple-mfd created from the grf node. Some settings are not used by anything but will need to be set up according to expectations on the kernel side. Best example is the force_jtag setting, which defaults to on and results in the soc switching the pin-outputs between jtag and sdmmc automatically depending on the card-detect status. This conflicts heavily with how the dw_mmc driver expects to do its work and also with the clock-controller, which has most likely deactivated the jtag clock due to it being unused. So far the handling of this setting was living in the mach-rockchip code for the arm32-based rk3288 but that of course doesn't work for arm64 socs and would also look ugly for further arm32 socs. Also always disabling this setting is quite specific to linux and its subsystems, other operating systems might prefer other settings, so that the bootloader cannot really set a sane default for all. So introduce a top-level driver for the grf that handles these settings that need to be a certain way but nobody cares about. Other needed settings might surface in the future and can then be added here, but only as a last option. Ideally general GRF settings should be handled in the driver needing them. Signed-off-by: Heiko Stuebner Reviewed-by: Douglas Anderson

soc: rockchip: power-domain: add power domain support for rk3328

2017-01-05T13:35:09+00:00

The rk3328 uses the newly introduced support for power-domain control in hiword-mask registers. Signed-off-by: Elaine Zhang Signed-off-by: Heiko Stuebner

soc: rockchip: power-domain: Support domain control in hiword-registers

2017-01-05T13:29:55+00:00

New Rockchips SoCs may have their power-domain control in registers using a writemask-based access scheme (upper 16bit being the write mask). So add a DOMAIN_M type and handle this case accordingly. Signed-off-by: Elaine Zhang Signed-off-by: Heiko Stuebner

soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecell

2016-11-11T01:14:59+00:00

It was a bit surprising that the device was reported to have probed just fine, but the provider hadn't been registered. So handle any errors when registering the provider and fail the probe accordingly. Signed-off-by: Tomeu Vizoso Cc: Caesar Wang Signed-off-by: Heiko Stuebner