kernel/linux.git/drivers/soc/rockchip/grf.c, branch linux-7.0.y

soc: rockchip: grf: Add missing of_node_put() when returning

2026-02-22T22:27:20+00:00

Fix the smatch checking: drivers/soc/rockchip/grf.c:249 rockchip_grf_init() warn: inconsistent refcounting 'np->kobj.kref.refcount.refs.counter': Reported-by: Dan Carpenter Fixes: 75fb63ae0312 ("soc: rockchip: grf: Support multiple grf to be handled") Closes: https://lore.kernel.org/all/aYXvgTcUJWQL2can@stanley.mountain/ Signed-off-by: Shawn Lin Link: https://patch.msgid.link/1770814957-17762-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner

soc: rockchip: grf: Support multiple grf to be handled

2026-01-16T10:33:50+00:00

Currently, only the first matched node will be handled. This leads to jtag switching broken for RK3576, as rk3576-sys-grf is found before rk3576-ioc-grf. Change the code to scan all the possible node to fix the problem. Fixes: e1aaecacfa13 ("soc: rockchip: grf: Add rk3576 default GRF values") Cc: stable@vger.kernel.org Cc: Detlev Casanova Signed-off-by: Shawn Lin Tested-by: Marco Schirrmeister Link: https://patch.msgid.link/1768524932-163929-3-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner

soc: rockchip: grf: Fix wrong RK3576_IOCGRF_MISC_CON definition

2026-01-16T10:33:50+00:00

RK3576_IOCGRF_MISC_CON is IOC_GRF + 0x40F0, fix it. Fixes: e1aaecacfa13 ("soc: rockchip: grf: Add rk3576 default GRF values") Cc: stable@vger.kernel.org Cc: Detlev Casanova Signed-off-by: Shawn Lin Reviewed-by: Chaoyi Chen Tested-by: Marco Schirrmeister Link: https://patch.msgid.link/1768524932-163929-2-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner

soc: rockchip: grf: Add select correct PWM implementation on RK3368

2025-11-17T21:34:12+00:00

Similar to the RK3288, the RK3368 has two different implementations of the PWM block inside the SoC - the newer ones that we have a driver for and that is used on every SoC and a previous variant that was likely left as a fallback if the new one creates problems. The devicetree is already set up for the new variant, so make sure we actually use it - similar to the RK3288. Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20251021074254.87065-4-heiko@sntech.de Signed-off-by: Heiko Stuebner

soc: rockchip: grf: Set pwm2/xin32k pad default to xin32k for rk3368

2025-10-21T09:19:53+00:00

PWM2 and xin32k share the same pad, but some peripheral need the xin32k clock to run properly, such as tsadc. I have observed that this pad is used as xin32k by default on some existing board [1], so it maybe more appropriate to set it to xin32k by default. I also tested it on another rk3368 based board [2], without this adjust, tsadc does not work properly. [1] https://rockchip.fr/geekbox/Geekbox_V1.23.pdf [2] https://ieiao.github.io/wiki/embedded-dev/rockchip/rk3368 Signed-off-by: WeiHao Li Link: https://patch.msgid.link/20250906142125.7602-1-cn.liweihao@gmail.com Signed-off-by: Heiko Stuebner

soc: rockchip: grf: switch to FIELD_PREP_WM16_CONST macro

2025-09-02T23:59:37+00:00

The era of hand-rolled HIWORD_UPDATE macros is over, at least for those drivers that use constant masks. Switch the rockchip grf driver to the FIELD_PREP_WM16_CONST macro, which brings with it more error checking while still being able to be used in initializers. All HIWORD_UPDATE instances and its definition are removed from the driver, as the conversion here is obvious, and static_asserts were used during development to make sure the ones greater than one bit in width were really equivalent. Signed-off-by: Nicolas Frattaroli Reviewed-by: Heiko Stuebner Signed-off-by: Yury Norov (NVIDIA)

soc: rockchip: grf: Add rk3576 default GRF values

2024-08-23T10:33:58+00:00

Set SW controlled i3c weak pull up and disable JTAG function on SDMMC IO. The i3c weak pull up is activated to let all gpio banks be controlled by the pinctrl driver. Disabling the JTAG function lets the SDMMC core use its full IO width. Signed-off-by: Detlev Casanova Acked-by: Dragan Simic Link: https://lore.kernel.org/r/20240822195706.920567-3-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner

soc: rockchip: grf: Set RK3128's vpu main clock

2024-08-23T09:52:53+00:00

RK3128 has a setting in GRF which selects whether the vpu attached iommu uses the AXI clock of the decoder (vdpu) or the encoder (vepu). The default is vepu but some part of the vendor firmware sets it to vdpu. In order to be independent on whether any of those vendor firmware blobs is used to boot the SoC reset "vpu main clock" setting to it's default value. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20240523185633.71355-3-knaerzche@gmail.com Signed-off-by: Heiko Stuebner

Merge tag 'soc-arm-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2023-08-30T23:49:40+00:00

Pull ARM SoC cleanups from Arnd Bergmann: "These are all minor cleanups for platform specific code in arch/arm/ and some of the associated drivers. The majority of these are work done by Rob Herring to improve the way devicetreee header files are handled" * tag 'soc-arm-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (49 commits) ARM: davinci: Drop unused includes ARM: s5pv210: Explicitly include correct DT includes ARM: dove: Drop unused includes ARM: mvebu: Explicitly include correct DT includes Documentation/process: maintainer-soc: document dtbs_check requirement for Samsung MAINTAINER: samsung: document dtbs_check requirement for Samsung Documentation/process: maintainer-soc: add clean platforms profile MAINTAINERS: soc: reference maintainer profile ARM: nspire: Remove unused header file mmio.h ARM: nspire: Use syscon-reboot to handle restart soc: fsl: Explicitly include correct DT includes soc: xilinx: Explicitly include correct DT includes soc: sunxi: Explicitly include correct DT includes soc: rockchip: Explicitly include correct DT includes soc: mediatek: Explicitly include correct DT includes soc: aspeed: Explicitly include correct DT includes firmware: Explicitly include correct DT includes bus: Explicitly include correct DT includes ARM: spear: Explicitly include correct DT includes ARM: mvebu: Explicitly include correct DT includes ...

soc: rockchip: grf: Fix SDMMC not working on RK3588 with bus-width > 1

2023-08-16T21:26:49+00:00

RK3588 has the same issue as other earlier RK SoCs. JTAG functionality muxed to some SDMMC data pins causes issues with SDMMC interface. Without this patch, I can only use SDMMC inteface with bus-width = <1>. (JTAG is muxed to data pins D2 and D3) Signed-off-by: Ondrej Jirman Link: https://lore.kernel.org/r/20230619011002.2249960-1-megi@xff.cz Signed-off-by: Heiko Stuebner