kernel/linux.git/drivers/soc/renesas, branch v6.6.141

soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM

2023-10-26T07:42:38+00:00

ARCH_R9A07G043 has its own non-standard global pool based DMA coherent allocator, which conflicts with the remap based RISCV_ISA_ZICBOM version. Add a proper dependency. Signed-off-by: Christoph Hellwig Reviewed-by: Lad Prabhakar Acked-by: Conor Dooley Acked-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231018052654.50074-4-hch@lst.de Signed-off-by: Geert Uytterhoeven

soc: renesas: Make ARCH_R9A07G043 depend on required options

2023-10-12T17:46:49+00:00

Randy reported a randconfig build issue against linux-next: WARNING: unmet direct dependencies detected for ERRATA_ANDES Depends on [n]: RISCV_ALTERNATIVE [=n] && RISCV_SBI [=y] Selected by [y]: - ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y] && NONPORTABLE [=y] && RISCV_SBI [=y] ../arch/riscv/errata/andes/errata.c:59:54: warning: 'struct alt_entry' declared inside parameter list will not be visible outside of this definition or declaration 59 | void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, On RISC-V, alternatives are not usable in XIP kernels, which this randconfig happened to select. Rather than add a check for whether alternatives are available before selecting the ERRATA_ANDES config option, rework the R9A07G043 Kconfig entry to depend on the configuration options required to support its non-standard cache coherency implementation. Without these options enabled, the SoC is effectively non-functional to begin with, so there's an extra benefit in preventing the creation of non-functional kernels. The "if RISCV_DMA_NONCOHERENT" can be dropped, as ERRATA_ANDES_CMO will select it. Reported-by: Randy Dunlap Closes: https://lore.kernel.org/all/09a6b0f0-76a1-45e3-ab52-329c47393d1d@infradead.org/ Signed-off-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231012-pouch-parkway-7d26c04b3300@spud Signed-off-by: Geert Uytterhoeven

soc: renesas: Make ARCH_R9A07G043 (riscv version) depend on NONPORTABLE

2023-10-05T13:07:57+00:00

Drew found "CONFIG_DMA_GLOBAL_POOL=y causes ADMA buffer alloc to fail" the log looks like: mmc0: Unable to allocate ADMA buffers - falling back to standard DMA The logic is: generic riscv defconfig selects ARCH_RENESAS then ARCH_R9A07G043 which selects DMA_GLOBAL_POOL, which assumes all non-dma-coherent riscv platforms have a dma global pool, this assumption seems not correct. And I believe DMA_GLOBAL_POOL should not be selected by ARCH_SOCFAMILIY, instead, only ARCH under some specific conditions can select it globaly, for example NOMMU ARM and so on, because it's designed for special cases such as "nommu cases where non-cacheable memory lives in a fixed place in the physical address map" as pointed out by Robin. Fix the issue by making ARCH_R9A07G043 (riscv version) depend on NONPORTABLE, thus generic defconfig won't select ARCH_R9A07G043 by default. And even for random config case, there will be less debug effort once we see NONPORTABLE is enabled. Reported-by: Drew Fustini Closes: https://lore.kernel.org/linux-riscv/ZRuamJuShOnvP1pr@x1/ Fixes: 484861e09f3e ("soc: renesas: Kconfig: Select the required configs for RZ/Five SoC") Signed-off-by: Jisheng Zhang Reviewed-by: Robin Murphy Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Tested-by: Drew Fustini Link: https://lore.kernel.org/r/20231004150856.2540-1-jszhang@kernel.org Signed-off-by: Geert Uytterhoeven

soc: renesas: Kconfig: For ARCH_R9A07G043 select the required configs if dependencies are met

2023-09-08T18:25:29+00:00

To prevent randconfig build issues when enabling the RZ/Five SoC, consider selecting specific configurations only when their dependencies are satisfied. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202308311610.ec6bm2G8-lkp@intel.com/ Signed-off-by: Lad Prabhakar Fixes: 484861e09f3e ("soc: renesas: Kconfig: Select the required configs for RZ/Five SoC") Reviewed-by: Geert Uytterhoeven Acked-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230901110936.313171-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt

Merge patch series "Add non-coherent DMA support for AX45MP"

2023-09-08T18:24:34+00:00

Prabhakar says: From: Lad Prabhakar non-coherent DMA support for AX45MP ==================================== On the Andes AX45MP core, cache coherency is a specification option so it may not be supported. In this case DMA will fail. To get around with this issue this patch series does the below: 1] Andes alternative ports is implemented as errata which checks if the IOCP is missing and only then applies to CMO errata. One vendor specific SBI EXT (ANDES_SBI_EXT_IOCP_SW_WORKAROUND) is implemented as part of errata. Below are the configs which Andes port provides (and are selected by RZ/Five): - ERRATA_ANDES - ERRATA_ANDES_CMO OpenSBI patch supporting ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI is now part v1.3 release. 2] Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. OpenSBI configures the PMA regions as required and creates a reserve memory node and propagates it to the higher boot stack. Currently OpenSBI (upstream) configures the required PMA region and passes this a shared DMA pool to Linux. reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; The above shared DMA pool gets appended to Linux DTB so the DMA memory requests go through this region. 3] We provide callbacks to synchronize specific content between memory and cache. 4] RZ/Five SoC selects the below configs - AX45MP_L2_CACHE - DMA_GLOBAL_POOL - ERRATA_ANDES - ERRATA_ANDES_CMO ----------x---------------------x--------------------x---------------x---- * b4-shazam-merge: soc: renesas: Kconfig: Select the required configs for RZ/Five SoC cache: Add L2 cache management for Andes AX45MP RISC-V core dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller riscv: mm: dma-noncoherent: nonstandard cache operations support riscv: errata: Add Andes alternative ports riscv: asm: vendorid_list: Add Andes Technology to the vendors list Link: https://lore.kernel.org/r/20230818135723.80612-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt

soc: renesas: Kconfig: Select the required configs for RZ/Five SoC

2023-09-01T16:09:00+00:00

Explicitly select the required Cache management and Errata configs required for the RZ/Five SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Acked-by: Geert Uytterhoeven Tested-by: Conor Dooley # tyre-kicking on a d1 Link: https://lore.kernel.org/r/20230818135723.80612-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt

soc: renesas: Move power-domain drivers to the genpd dir

2023-07-14T08:40:56+00:00

To simplify with maintenance let's move the renesas power-domain drivers to the new genpd directory. Going forward, patches are intended to be managed through a separate git tree, according to MAINTAINERS. Cc: Geert Uytterhoeven Cc: Magnus Damm Cc: Signed-off-by: Ulf Hansson

soc: renesas: rmobile-sysc: Convert to readl_poll_timeout_atomic()

2023-06-05T13:43:27+00:00

Use readl_poll_timeout_atomic() instead of open-coding the same operation. 1. rmobile_pd_power_down(): as typically less than 20 retries are needed, PSTR_RETRIES (100) µs is a suitable timeout value. 2. __rmobile_pd_power_up(): the old method of first polling some cycles with a 1 µs delay, followed by more polling cycles without any delay didn't make much sense, as the latter was insignificant compared to the former. Furthermore, typically no retries are needed. Hence just retain the polling with delay. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/ae4bf03ab8fd5a557c683086958d6764babc0723.1685692810.git.geert+renesas@glider.be

soc: renesas: rcar-rst: Allow WDT reset on R-Car V3U

2023-05-15T08:32:12+00:00

V3U firmware misses to enable WDT resets. Because there won't be any updates to the firmware anymore, enable that in Linux. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230419201511.31648-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven

soc: renesas: renesas-soc: Release 'chipid' from ioremap()

2023-04-04T08:01:58+00:00

Smatch reports: drivers/soc/renesas/renesas-soc.c:536 renesas_soc_init() warn: 'chipid' from ioremap() not released on lines: 475. If soc_dev_atrr allocation is failed, function renesas_soc_init() will return without releasing 'chipid' from ioremap(). Fix this by adding function iounmap(). Fixes: cb5508e47e60 ("soc: renesas: Add support for reading product revision for RZ/G2L family") Signed-off-by: Li Yang Reviewed-by: Dan Carpenter Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230331095545.31823-1-lidaxian@hust.edu.cn Signed-off-by: Geert Uytterhoeven