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<title>kernel/linux.git/drivers/reset/reset-mpfs.c, branch v6.1.174</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.174</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.174'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2022-09-14T07:55:17+00:00</updated>
<entry>
<title>reset: add polarfire soc reset support</title>
<updated>2022-09-14T07:55:17+00:00</updated>
<author>
<name>Conor Dooley</name>
<email>conor.dooley@microchip.com</email>
</author>
<published>2022-09-09T12:31:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=05f9e36370c1517c8e03325f38910fd7ad30b177'/>
<id>urn:sha1:05f9e36370c1517c8e03325f38910fd7ad30b177</id>
<content type='text'>
Add support for the resets on Microchip's PolarFire SoC (MPFS).
Reset control is a single register, wedged in between registers for
clock control. To fit with existed DT etc, the reset controller is
created using the aux device framework &amp; set up in the clock driver.

Reviewed-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Reviewed-by: Daire McNamara &lt;daire.mcnamara@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Link: https://lore.kernel.org/r/20220909123123.2699583-6-conor.dooley@microchip.com
</content>
</entry>
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