kernel/linux.git/drivers/ras/amd, branch v7.2-rc1

Merge tag 'edac_updates_for_v7.2_rc1' of gitolite.kernel.org:pub/scm/linux/kernel/git/ras/ras

2026-06-16T00:01:01+00:00

Pull EDAC updates from Borislav Petkov: - Fix a malformed Kconfig default for the AMD Address Translation Library - Make sure i10nm loads successfully when the ADXL address decoder is absent because former has decoding capabilities too - Ensure error reporting is cleanly disabled on driver teardown and on failed initialization for several legacy Intel EDAC drivers - Fix a grammar issue in a diagnostic warning in the Sandy Bridge driver - Fix a missing resource release callback and incorrect memory topology parsing in the igen6 driver, and add support for Intel Panther Lake-H and Nova Lake-H SoCs - Fix an out-of-bounds shift causing undefined behaviour in the Skylake driver - Consolidate memory controller register access helpers into shared common code across the Intel Skylake, Ice Lake, and Meteor Lake drivers - Introduce sub-channel awareness and Rank Retry Logic improvements to the Intel Skylake and i10nm drivers in preparation for Diamond Rapids server support - Add Rank Retry Logic support for Intel Diamond Rapids server to imh_edac - Make In-Band ECC detection registers configurable per SoC in the igen6 driver - Standardize PCI device ID table definitions across all EDAC drivers to use named field initializers and standard PCI helper macros * tag 'edac_updates_for_v7.2_rc1' of gitolite.kernel.org:pub/scm/linux/kernel/git/ras/ras: (22 commits) EDAC: Consistently define pci_device_ids using named initializers EDAC/igen6: Add Intel Nova Lake-H SoC support EDAC/igen6: Make registers for detecting IBECC configurable EDAC/imh: Add RRL support for Intel Diamond Rapids server EDAC/{skx_common,i10nm}: Prepare RRL for sub-channel granularity EDAC/skx_common: Add SubChannel support to ADXL decode EDAC/{skx_common,i10nm}: Move RRL handling to common code EDAC/{skx_common,i10nm}: Introduce rrl_ctrl_mode EDAC/{skx_common,i10nm}: Rename rrl_mode to rrl_source_type EDAC/{skx_common,skx,i10nm}: Split skx_set_decode() EDAC/{skx_common,i10nm,imh}: Move MC register access helpers to skx_common EDAC/{skx_common,skx}: Fix UBSAN shift-out-of-bounds in skx_get_dimm_info EDAC/igen6: Add one Intel Panther Lake-H SoC support EDAC/igen6: Fix memory topology parsing for Panther Lake-H SoCs EDAC/igen6: Fix call trace due to missing release() EDAC/sb_edac: fix grammar in sb_decode_ddr3 warning EDAC/i5400: disable error reporting at teardown and refactor helper EDAC/i5100: disable error reporting at teardown and create helper EDAC/i5000: disable error reporting at teardown and refactor helper EDAC/i7300: disable error reporting if init fails and refactor helper ...

RAS/AMD/ATL: Drop malformed default N from Kconfig

2026-05-14T11:24:51+00:00

The capital letters are for symbols and N in 'default N' will be evaluated as another, nonexistent, Kconfig symbol, and not as the 'no' it should be. More importantly, 'n' *is* the default already. Hence just drop the malformed line. Signed-off-by: Andy Shevchenko Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260513205021.368190-1-andriy.shevchenko@linux.intel.com

treewide: Explicitly include the x86 CPUID headers

2026-05-06T12:29:59+00:00

Modify all CPUID call sites which implicitly include any of the CPUID headers to explicitly include them instead. For KVM's reverse_cpuid.h, just include since it references the CPUID_EAX..EDX symbols without using the CPUID APIs. Note, this allows removing the inclusion of from within next. That allows the CPUID API headers to include without introducing a circular dependency. Signed-off-by: Ahmed S. Darwish Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/20260327021645.555257-1-darwi@linutronix.de

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-22T01:09:51+00:00

This was done entirely with mindless brute force, using git grep -l '\

treewide: Replace kmalloc with kmalloc_obj for non-scalar types

2026-02-21T09:02:28+00:00

This is the result of running the Coccinelle script from scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to avoid scalar types (which need careful case-by-case checking), and instead replace kmalloc-family calls that allocate struct or union object instances: Single allocations: kmalloc(sizeof(TYPE), ...) are replaced with: kmalloc_obj(TYPE, ...) Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...) are replaced with: kmalloc_objs(TYPE, COUNT, ...) Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...) are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...) (where TYPE may also be *VAR) The resulting allocations no longer return "void *", instead returning "TYPE *". Signed-off-by: Kees Cook

RAS/AMD/ATL: Remove an unneeded semicolon

2025-12-29T14:30:02+00:00

Remove an unneeded semicolon. No functional changes. Detected by Coccinelle. Signed-off-by: Chen Ni Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20240701072118.846277-1-nichen@iscas.ac.cn

RAS/AMD/ATL: Replace bitwise_xor_bits() with hweight16()

2025-11-24T16:00:37+00:00

Doing hweight16() and checking whether the lsb is set is functionally equivalent to what bitwise_xor_bits() does. In addition, it results in better generated code as before gcc would inline the function 4 times. With hweight16(), the resulting code boils down to 2 instructions - POPCNT and AND, and all relevant CPUs support POPCNT. An alternative would have been to use the __builtin_parity() function provided by both Clang/GCC, however under some circumstances the compiler can choose not to inline it but generate a library call which is unsupported in the kernel. No functional changes. [ bp: Massage commit message. ] Signed-off-by: Nikolay Borisov Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20251124142517.1708451-1-nik.borisov@suse.com

RAS/AMD/ATL: Require PRM support for future systems

2025-10-27T18:56:41+00:00

Currently, the AMD Address Translation Library will fail to load for new, unrecognized systems (based on Data Fabric revision). The intention is to prevent the code from executing on new systems and returning incorrect results. Recent AMD systems, however, may provide UEFI PRM handlers for address translation. This is code provided by the platform through BIOS tables. These are the preferred method for translation, and the Linux native code can be used as a fallback. Future AMD systems are expected to provide PRM handlers by default. And Linux native code will not be used. Adjust the ATL init code so that new, unrecognized systems will default to using PRM handlers only. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Reviewed-by: "Mario Limonciello (AMD)" Link: https://patch.msgid.link/all/20251017-wip-atl-prm-v2-2-7ab1df4a5fbc@amd.com

RAS/AMD/ATL: Return error codes from helper functions

2025-10-17T12:38:42+00:00

Pass up error codes from helper functions rather than discarding them. Suggested-by: Mario Limonciello Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD)

Merge tag 'v6.15-rc5' into x86/cpu, to resolve conflicts

2025-05-06T08:00:58+00:00

Conflicts: tools/arch/x86/include/asm/cpufeatures.h Signed-off-by: Ingo Molnar