kernel/linux.git/drivers/ras/amd, branch v6.19.11

RAS/AMD/ATL: Replace bitwise_xor_bits() with hweight16()

2025-11-24T16:00:37+00:00

Doing hweight16() and checking whether the lsb is set is functionally equivalent to what bitwise_xor_bits() does. In addition, it results in better generated code as before gcc would inline the function 4 times. With hweight16(), the resulting code boils down to 2 instructions - POPCNT and AND, and all relevant CPUs support POPCNT. An alternative would have been to use the __builtin_parity() function provided by both Clang/GCC, however under some circumstances the compiler can choose not to inline it but generate a library call which is unsupported in the kernel. No functional changes. [ bp: Massage commit message. ] Signed-off-by: Nikolay Borisov Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20251124142517.1708451-1-nik.borisov@suse.com

RAS/AMD/ATL: Require PRM support for future systems

2025-10-27T18:56:41+00:00

Currently, the AMD Address Translation Library will fail to load for new, unrecognized systems (based on Data Fabric revision). The intention is to prevent the code from executing on new systems and returning incorrect results. Recent AMD systems, however, may provide UEFI PRM handlers for address translation. This is code provided by the platform through BIOS tables. These are the preferred method for translation, and the Linux native code can be used as a fallback. Future AMD systems are expected to provide PRM handlers by default. And Linux native code will not be used. Adjust the ATL init code so that new, unrecognized systems will default to using PRM handlers only. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Reviewed-by: "Mario Limonciello (AMD)" Link: https://patch.msgid.link/all/20251017-wip-atl-prm-v2-2-7ab1df4a5fbc@amd.com

RAS/AMD/ATL: Return error codes from helper functions

2025-10-17T12:38:42+00:00

Pass up error codes from helper functions rather than discarding them. Suggested-by: Mario Limonciello Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD)

Merge tag 'v6.15-rc5' into x86/cpu, to resolve conflicts

2025-05-06T08:00:58+00:00

Conflicts: tools/arch/x86/include/asm/cpufeatures.h Signed-off-by: Ingo Molnar

x86/platform/amd: Move the header to

2025-04-14T07:34:17+00:00

Collect AMD specific platform header files in . Signed-off-by: Ingo Molnar Acked-by: Borislav Petkov (AMD) Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Mario Limonciello Link: https://lore.kernel.org/r/20250413084144.3746608-7-mingo@kernel.org

x86/platform/amd: Move the header to

2025-04-14T07:34:14+00:00

RAS/AMD/FMPM: Get masked address

2025-04-08T17:30:58+00:00

Some operations require checking, or ignoring, specific bits in an address value. For example, this can be comparing address values to identify unique structures. Currently, the full address value is compared when filtering for duplicates. This results in over counting and creation of extra records. This gives the impression that more unique events occurred than did in reality. Mask the address for physical rows on MI300. [ bp: Simplify. ] Fixes: 6f15e617cc99 ("RAS: Introduce a FRU memory poison manager") Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Cc: stable@vger.kernel.org

RAS/AMD/ATL: Include row[13] bit in row retirement

2025-04-07T13:06:06+00:00

Based on feedback from hardware folks, row[13] is part of the variable bits within a physical row (along with all column bits). Only half the physical addresses affected by a row are calculated if this bit is not included. Add the row[13] bit to the row retirement flow. Fixes: 3b566b30b414 ("RAS/AMD/ATL: Add MI300 row retirement support") Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250401-fix-fmpm-extra-records-v1-1-840bcf7a8ac5@amd.com

x86/amd_nb: Move SMN access code to a new amd_node driver

2025-01-08T09:59:44+00:00

SMN access was bolted into amd_nb mostly as convenience. This has limitations though that require incurring tech debt to keep it working. Move SMN access to the newly introduced AMD Node driver. Signed-off-by: Mario Limonciello Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Acked-by: Ilpo Järvinen # pdx86 Acked-by: Shyam Sundar S K # PMF, PMC Link: https://lore.kernel.org/r/20241206161210.163701-11-yazen.ghannam@amd.com

RAS/AMD/ATL: Add debug prints for DF register reads

2024-10-22T16:55:57+00:00

The ATL will fail early if the DF register access fails due to missing PCI IDs in the amd_nb code. There aren't any clear indicators on why the ATL will fail to load in this case. Add a couple of debug print statements to highlight reasons for failure. A common scenario is missing support for new hardware. If the ATL fails to load on a system, and there is interest to support it, then dynamic debugging can be enabled to help find the cause for failure. If there is no interest in supporting ATL on a new system, then these failures will be silent. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20241021152158.2525669-1-yazen.ghannam@amd.com