kernel/linux.git/drivers/ptp/Makefile, branch v6.1.168

ptp: add ptp virtual clock driver framework

2021-07-01T20:08:18+00:00

This patch is to add ptp virtual clock driver framework utilizing timecounter/cyclecounter. The patch just exports two essential APIs for PTP driver. - ptp_vclock_register() - ptp_vclock_unregister() Signed-off-by: Yangbo Lu Signed-off-by: David S. Miller

ptp: arm/arm64: Enable ptp_kvm for arm/arm64

2021-04-07T15:33:20+00:00

Currently, there is no mechanism to keep time sync between guest and host in arm/arm64 virtualization environment. Time in guest will drift compared with host after boot up as they may both use third party time sources to correct their time respectively. The time deviation will be in order of milliseconds. But in some scenarios,like in cloud environment, we ask for higher time precision. kvm ptp clock, which chooses the host clock source as a reference clock to sync time between guest and host, has been adopted by x86 which takes the time sync order from milliseconds to nanoseconds. This patch enables kvm ptp clock for arm/arm64 and improves clock sync precision significantly. Test result comparisons between with kvm ptp clock and without it in arm/arm64 are as follows. This test derived from the result of command 'chronyc sources'. we should take more care of the last sample column which shows the offset between the local clock and the source at the last measurement. no kvm ptp in guest: MS Name/IP address Stratum Poll Reach LastRx Last sample ======================================================================== ^* dns1.synet.edu.cn 2 6 377 13 +1040us[+1581us] +/- 21ms ^* dns1.synet.edu.cn 2 6 377 21 +1040us[+1581us] +/- 21ms ^* dns1.synet.edu.cn 2 6 377 29 +1040us[+1581us] +/- 21ms ^* dns1.synet.edu.cn 2 6 377 37 +1040us[+1581us] +/- 21ms ^* dns1.synet.edu.cn 2 6 377 45 +1040us[+1581us] +/- 21ms ^* dns1.synet.edu.cn 2 6 377 53 +1040us[+1581us] +/- 21ms ^* dns1.synet.edu.cn 2 6 377 61 +1040us[+1581us] +/- 21ms ^* dns1.synet.edu.cn 2 6 377 4 -130us[ +796us] +/- 21ms ^* dns1.synet.edu.cn 2 6 377 12 -130us[ +796us] +/- 21ms ^* dns1.synet.edu.cn 2 6 377 20 -130us[ +796us] +/- 21ms in host: MS Name/IP address Stratum Poll Reach LastRx Last sample ======================================================================== ^* 120.25.115.20 2 7 377 72 -470us[ -603us] +/- 18ms ^* 120.25.115.20 2 7 377 92 -470us[ -603us] +/- 18ms ^* 120.25.115.20 2 7 377 112 -470us[ -603us] +/- 18ms ^* 120.25.115.20 2 7 377 2 +872ns[-6808ns] +/- 17ms ^* 120.25.115.20 2 7 377 22 +872ns[-6808ns] +/- 17ms ^* 120.25.115.20 2 7 377 43 +872ns[-6808ns] +/- 17ms ^* 120.25.115.20 2 7 377 63 +872ns[-6808ns] +/- 17ms ^* 120.25.115.20 2 7 377 83 +872ns[-6808ns] +/- 17ms ^* 120.25.115.20 2 7 377 103 +872ns[-6808ns] +/- 17ms ^* 120.25.115.20 2 7 377 123 +872ns[-6808ns] +/- 17ms The dns1.synet.edu.cn is the network reference clock for guest and 120.25.115.20 is the network reference clock for host. we can't get the clock error between guest and host directly, but a roughly estimated value will be in order of hundreds of us to ms. with kvm ptp in guest: chrony has been disabled in host to remove the disturb by network clock. MS Name/IP address Stratum Poll Reach LastRx Last sample ======================================================================== * PHC0 0 3 377 8 -7ns[ +1ns] +/- 3ns * PHC0 0 3 377 8 +1ns[ +16ns] +/- 3ns * PHC0 0 3 377 6 -4ns[ -0ns] +/- 6ns * PHC0 0 3 377 6 -8ns[ -12ns] +/- 5ns * PHC0 0 3 377 5 +2ns[ +4ns] +/- 4ns * PHC0 0 3 377 13 +2ns[ +4ns] +/- 4ns * PHC0 0 3 377 12 -4ns[ -6ns] +/- 4ns * PHC0 0 3 377 11 -8ns[ -11ns] +/- 6ns * PHC0 0 3 377 10 -14ns[ -20ns] +/- 4ns * PHC0 0 3 377 8 +4ns[ +5ns] +/- 4ns The PHC0 is the ptp clock which choose the host clock as its source clock. So we can see that the clock difference between host and guest is in order of ns. Cc: Mark Rutland Acked-by: Richard Cochran Signed-off-by: Jianyong Wu Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20201209060932.212364-8-jianyong.wu@arm.com

ptp: Reorganize ptp_kvm.c to make it arch-independent

2021-04-07T15:33:07+00:00

Currently, the ptp_kvm module contains a lot of x86-specific code. Let's move this code into a new arch-specific file in the same directory, and rename the arch-independent file to ptp_kvm_common.c. Acked-by: Richard Cochran Reviewed-by: Andre Przywara Signed-off-by: Jianyong Wu Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20201209060932.212364-4-jianyong.wu@arm.com

ptp: Add clock driver for the OpenCompute TimeCard.

2020-12-05T21:59:41+00:00

The OpenCompute time card is an atomic clock along with a GPS receiver that provides a Grandmaster clock source for a PTP enabled network. More information is available at http://www.timingcard.com/ Signed-off-by: Jonathan Lemon Acked-by: Richard Cochran Link: https://lore.kernel.org/r/20201204035128.2219252-2-jonathan.lemon@gmail.com Signed-off-by: Jakub Kicinski

ptp: add VMware virtual PTP clock driver

2020-03-06T01:25:07+00:00

Add a PTP clock driver called ptp_vmw, for guests running on VMware ESXi hypervisor. The driver attaches to a VMware virtual device called "precision clock" that provides a mechanism for querying host system time. Similar to existing virtual PTP clock drivers (e.g. ptp_kvm), ptp_vmw utilizes the kernel's PTP hardware clock API to implement a clock device that can be used as a reference in Chrony for synchronizing guest time with host. The driver is only applicable to x86 guests running in VMware virtual machines with precision clock virtual device present. It uses a VMware specific hypercall mechanism to read time from the device. Reviewed-by: Thomas Hellstrom Signed-off-by: Vivek Thampi Signed-off-by: David S. Miller

ptp: Add a ptp clock driver for IDT 82P33 SMU.

2020-02-24T21:08:46+00:00

The IDT 82P33 Synchronization Management Unit (SMU) family provides tools to manage timing references, clock sources and timing paths for IEEE 1588 / Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: PTP clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). This patch adds support for ptp clock based on the device. Changes since v1: - As suggested by Richard Cochran: 1. Replace _mask_bit_count with the existing hweight8 2. Prefix all functions with idt82p33 3. Fix white space issues in Kconfig and Makefile 4. Remove forward declaration 5. Use adjfine instead of adjfreq for better resolution - As suggested by David Miller: 1. Replace CHAN_INIT macro with a static function idt82p33_channel_init 2. Employ reverse christmas tree ordering for local variables 3. Fix indentation problem by appropriate number of TAB then SPACE character Signed-off-by: Min Li Signed-off-by: David S. Miller

ptp: ixp46x: move adjacent to ethernet driver

2020-01-12T20:59:52+00:00

The ixp46x ptp driver has a somewhat unusual setup, where the ptp driver and the ethernet driver are in different directories but access the same registers that are defined a platform specific header file. Moving everything into drivers/net/ makes it look more like most other ptp drivers and allows compile-testing this driver on other targets. Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij Signed-off-by: Jakub Kicinski

ptp: Add a driver for InES time stamping IP core.

2019-12-26T03:51:34+00:00

The InES at the ZHAW offers a PTP time stamping IP core. The FPGA logic recognizes and time stamps PTP frames on the MII bus. This patch adds a driver for the core along with a device tree binding to allow hooking the driver to MII buses. Signed-off-by: Richard Cochran Signed-off-by: David S. Miller

ptp: Add a ptp clock driver for IDT ClockMatrix.

2019-11-04T01:35:40+00:00

The IDT ClockMatrix (TM) family includes integrated devices that provide eight PLL channels. Each PLL channel can be independently configured as a frequency synthesizer, jitter attenuator, digitally controlled oscillator (DCO), or a digital phase lock loop (DPLL). Typically these devices are used as timing references and clock sources for PTP applications. This patch adds support for the device. Co-developed-by: Richard Cochran Signed-off-by: Richard Cochran Signed-off-by: Vincent Cheng Signed-off-by: David S. Miller

ptp: add debugfs support for ptp_qoriq

2019-01-23T04:21:57+00:00

This patch is to add debugfs support for ptp_qoriq. Current debugfs supports to control fiper1/fiper2 loopback mode. If the loopback mode is enabled, the fiper1/fiper2 pulse is looped back into trigger1/ trigger2 input. This is very useful for validating hardware and driver without external hardware. Below is an example to enable fiper1 loopback. echo 1 > /sys/kernel/debug/2d10e00.ptp_clock/fiper1-loopback Signed-off-by: Yangbo Lu Signed-off-by: David S. Miller