kernel/linux.git/drivers/pinctrl/tegra, branch v7.0-rc7

pinctrl: tegra-xusb: Simplify locking with guard()

2026-01-19T00:11:47+00:00

Simplify error handling (less gotos) over locks with guard(). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij

pinctrl: tegra-xusb: Return void in padctl enable/disable functions

2026-01-19T00:11:47+00:00

Make the padctl functions a bit simpler by returning void instead of always '0'. The callers - phy init/exit - still need to return 0, but these are smaller function without if/branching. Acked-by: Thierry Reding Reviewed-by: Jon Hunter Signed-off-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij

pinctrl: tegra20: register csus_mux clock

2025-10-14T12:02:57+00:00

Add csus_mux for further use as the csus clock parent, similar to how the cdev1 and cdev2 muxes are utilized. Additionally, constify the cdev parent name lists to resolve checkpatch warnings. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Signed-off-by: Linus Walleij

pinctrl: tegra: Add Tegra186 pinmux driver

2025-08-19T11:26:51+00:00

This is based on Nvidia's downstream 5.10 driver, rewritten to match the mainline Tegra194 pinmux driver. Signed-off-by: Aaron Kling Link: https://lore.kernel.org/20250812-tegra186-pinctrl-v3-2-115714eeecb1@gmail.com Signed-off-by: Linus Walleij

pinctrl: tegra: Fix off by one in tegra_pinctrl_get_group()

2025-03-20T08:12:44+00:00

This should be >= pmx->soc->ngroups instead of > to avoid an out of bounds access. The pmx->soc->groups[] array is allocated in tegra_pinctrl_probe(). Fixes: c12bfa0fee65 ("pinctrl-tegra: Restore SFSEL bit when freeing pins") Signed-off-by: Dan Carpenter Reviewed-by: Kunwu Chan Link: https://lore.kernel.org/82b40d9d-b437-42a9-9eb3-2328aa6877ac@stanley.mountain Signed-off-by: Linus Walleij

pinctrl: tegra: Set SFIO mode to Mux Register

2025-03-17T13:24:21+00:00

Tegra devices have an 'sfsel' bit field that determines whether a pin operates in SFIO (Special Function I/O) or GPIO mode. Currently, tegra_pinctrl_gpio_disable_free() sets this bit when releasing a GPIO. However, tegra_pinctrl_set_mux() can be called independently in certain code paths where gpio_disable_free() is not invoked. In such cases, failing to set the SFIO mode could lead to incorrect pin configurations, resulting in functional issues for peripherals relying on SFIO. This patch ensures that whenever set_mux() is called, the SFIO mode is correctly set in the Mux Register if the 'sfsel' bit is present. This prevents situations where the pin remains in GPIO mode despite being configured for SFIO use. Fixes: 971dac7123c7 ("pinctrl: add a driver for NVIDIA Tegra") Signed-off-by: Prathamesh Shete Link: https://lore.kernel.org/20250306050542.16335-1-pshete@nvidia.com Signed-off-by: Linus Walleij

pinctrl-tegra: Restore SFSEL bit when freeing pins

2025-03-14T10:03:49+00:00

Each pin can be configured as a Special Function IO (SFIO) or GPIO, where the SFIO enables the pin to operate in alternative modes such as I2C, SPI, etc. The current implementation sets all the pins back to SFIO mode even if they were initially in GPIO mode. This can cause glitches on the pins when pinctrl_gpio_free() is called. Avoid these undesired glitches by storing the pin's SFIO/GPIO state on GPIO request and restoring it on GPIO free. Signed-off-by: Prathamesh Shete Link: https://lore.kernel.org/20250305104939.15168-2-pshete@nvidia.com Signed-off-by: Linus Walleij

pinctrl: tegra: Add descriptions for SoC data fields

2025-03-14T10:03:49+00:00

Add detailed descriptions for the remaining fields in the tegra_pinctrl_soc_data structure. This improves code documentation and clarifies the purpose of each field, particularly for the pin-specific configuration options. Signed-off-by: Prathamesh Shete Link: https://lore.kernel.org/20250305104939.15168-1-pshete@nvidia.com Signed-off-by: Linus Walleij

pinctrl-tegra: Add config property GPIO mode

2025-02-28T08:37:25+00:00

The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing system: - When set to 1, the pin operates in SFIO mode, controlled by the pin's assigned special function. - When set to 0, the pin operates as a general-purpose GPIO. This SFIO/GPIO select bit that is set for a given pin is not displayed, adding the support to retrieve this information from the pinmux set for each pin. Signed-off-by: Prathamesh Shete Link: https://lore.kernel.org/20241217153249.5712-1-pshete@nvidia.com Signed-off-by: Linus Walleij

pinctrl: tegra: Use scope based of_node_put() cleanups

2024-06-26T09:55:34+00:00

Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan Acked-by: Thierry Reding Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-2-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij