kernel/linux.git/drivers/pinctrl/tegra, branch v6.6.132

pinctrl: tegra: Fix off by one in tegra_pinctrl_get_group()

2025-06-04T12:42:21+00:00

commit 5a062c3c3b82004766bc3ece82b594d337076152 upstream. This should be >= pmx->soc->ngroups instead of > to avoid an out of bounds access. The pmx->soc->groups[] array is allocated in tegra_pinctrl_probe(). Fixes: c12bfa0fee65 ("pinctrl-tegra: Restore SFSEL bit when freeing pins") Signed-off-by: Dan Carpenter Reviewed-by: Kunwu Chan Link: https://lore.kernel.org/82b40d9d-b437-42a9-9eb3-2328aa6877ac@stanley.mountain Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman

pinctrl-tegra: Restore SFSEL bit when freeing pins

2025-06-04T12:41:59+00:00

[ Upstream commit c12bfa0fee65940b10ff5187349f76c6f6b1df9c ] Each pin can be configured as a Special Function IO (SFIO) or GPIO, where the SFIO enables the pin to operate in alternative modes such as I2C, SPI, etc. The current implementation sets all the pins back to SFIO mode even if they were initially in GPIO mode. This can cause glitches on the pins when pinctrl_gpio_free() is called. Avoid these undesired glitches by storing the pin's SFIO/GPIO state on GPIO request and restoring it on GPIO free. Signed-off-by: Prathamesh Shete Link: https://lore.kernel.org/20250305104939.15168-2-pshete@nvidia.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: tegra: Set SFIO mode to Mux Register

2025-04-10T12:37:31+00:00

[ Upstream commit 17013f0acb322e5052ff9b9d0fab0ab5a4bfd828 ] Tegra devices have an 'sfsel' bit field that determines whether a pin operates in SFIO (Special Function I/O) or GPIO mode. Currently, tegra_pinctrl_gpio_disable_free() sets this bit when releasing a GPIO. However, tegra_pinctrl_set_mux() can be called independently in certain code paths where gpio_disable_free() is not invoked. In such cases, failing to set the SFIO mode could lead to incorrect pin configurations, resulting in functional issues for peripherals relying on SFIO. This patch ensures that whenever set_mux() is called, the SFIO mode is correctly set in the Mux Register if the 'sfsel' bit is present. This prevents situations where the pin remains in GPIO mode despite being configured for SFIO use. Fixes: 971dac7123c7 ("pinctrl: add a driver for NVIDIA Tegra") Signed-off-by: Prathamesh Shete Link: https://lore.kernel.org/20250306050542.16335-1-pshete@nvidia.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

Revert "pinctrl: tegra: Add support to display pin function"

2023-09-27T08:51:57+00:00

This reverts commit d1cd5b51bc9152dc2b63c5f843590272d6694d50. It was reported that some I2C3 functions stop working after this patch, and it is just debug help so let's revert it and investigate. Link: https://lore.kernel.org/linux-gpio/20230925183049.10a40546@booty/ Signed-off-by: Linus Walleij

Merge tag 'intel-pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

2023-08-25T13:47:18+00:00

intel-pinctrl for v6.6-1 * New library driver for Intel MID to deduplicate code (Raag Jadav) * Reuse common functions from pinctrl-intel to reduce the code (Raag Jadav) * Move most of the exported functions to the PINCTRL_INTEL namespace * Make use of pm_ptr() in Bay Trail and Lynxpoint drivers * Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper and use it in a few drivers * Consolidata ACPI dependency in Kconfig (Raag Jadav) * Fix address_space_handler() argument in Cherryview driver (Raag Jadav) * Optinmize byt_pin_config_set() to avoid IO in error cases (Raag Jadav) The following is an automated git shortlog grouped by driver: at91: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper baytrail: - Make use of pm_ptr() - reuse common functions from pinctrl-intel - consolidate common mask operation cherryview: - fix address_space_handler() argument - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper - reuse common functions from pinctrl-intel intel: - consolidate ACPI dependency - Switch to use exported namespace - export common pinctrl functions lynxpoint: - Make use of pm_ptr() - reuse common functions from pinctrl-intel Merge patch series: - Merge patch series "Introduce Intel Tangier pinctrl driver" - Merge patch series "Reuse common functions from pinctrl-intel" merrifield: - Adapt to Intel Tangier driver moorefield: - Adapt to Intel Tangier driver mvebu: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pm: - Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper renesas: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper tangier: - Introduce Intel Tangier driver tegra: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper Signed-off-by: Linus Walleij

pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper

2023-08-21T16:07:44+00:00

Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. With that, make sure the PM ops are used only in CONFIG_PM_SLEEP=y case by wrapping them in pm_sleep_ptr() macro. Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230717172821.62827-11-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko

pinctrl: Explicitly include correct DT includes

2023-07-20T19:41:24+00:00

The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Reviewed-by: Damien Le Moal Acked-by: Emil Renner Berthing Acked-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij

pinctrl: tegra: Add support to display pin function

2023-07-20T19:34:53+00:00

The current function for a given pin is not displayed via the debugfs. Add support to display the current function that is set for each pin. Signed-off-by: Prathamesh Shete Acked-by: Thierry Reding Reviewed-by: Jon Hunter Link: https://lore.kernel.org/r/20230714113547.15384-1-pshete@nvidia.com Signed-off-by: Linus Walleij

pinctrl: tegra: avoid duplicate field initializers

2023-06-19T08:54:35+00:00

The drv_reg field is initialized both in the DRV_PINGROUP_ENTRY_N/DRV_PINGROUP_ENTRY_Y macros and in DRV_PINGROUP_Y. Since each pingroup expands both macros, the are always duplicate and turning on -Woverride-init (which is disabled by default) causes a huge amount of warnings like: drivers/pinctrl/tegra/pinctrl-tegra234.c:1384:27: error: initialized field overwritten [-Werror=override-init] 1384 | #define DRV_PINGROUP_Y(r) ((r)) | ^ drivers/pinctrl/tegra/pinctrl-tegra234.c:1397:28: note: in expansion of macro 'DRV_PINGROUP_Y' 1397 | .drv_reg = DRV_PINGROUP_Y(r), \ | ^~~~~~~~~~~~~~ drivers/pinctrl/tegra/pinctrl-tegra234.c:1447:49: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y' 1447 | #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0) | ^~~~~~~~~~~~~~~~~~~~ ... Remove the intialization that is never used here. Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20230616161603.1127687-1-arnd@kernel.org Signed-off-by: Linus Walleij

pinctrl: tegra: Add Tegra234 pinmux driver

2023-06-09T07:14:44+00:00

This change adds support for the two pin controllers found on Tegra234. Signed-off-by: Prathamesh Shete Signed-off-by: Thierry Reding Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230605154230.2910847-3-thierry.reding@gmail.com Signed-off-by: Linus Walleij