kernel/linux.git/drivers/pinctrl/tegra, branch v6.12.80

pinctrl: tegra: Fix off by one in tegra_pinctrl_get_group()

2025-05-29T09:03:26+00:00

commit 5a062c3c3b82004766bc3ece82b594d337076152 upstream. This should be >= pmx->soc->ngroups instead of > to avoid an out of bounds access. The pmx->soc->groups[] array is allocated in tegra_pinctrl_probe(). Fixes: c12bfa0fee65 ("pinctrl-tegra: Restore SFSEL bit when freeing pins") Signed-off-by: Dan Carpenter Reviewed-by: Kunwu Chan Link: https://lore.kernel.org/82b40d9d-b437-42a9-9eb3-2328aa6877ac@stanley.mountain Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman

pinctrl-tegra: Restore SFSEL bit when freeing pins

2025-05-29T09:02:18+00:00

[ Upstream commit c12bfa0fee65940b10ff5187349f76c6f6b1df9c ] Each pin can be configured as a Special Function IO (SFIO) or GPIO, where the SFIO enables the pin to operate in alternative modes such as I2C, SPI, etc. The current implementation sets all the pins back to SFIO mode even if they were initially in GPIO mode. This can cause glitches on the pins when pinctrl_gpio_free() is called. Avoid these undesired glitches by storing the pin's SFIO/GPIO state on GPIO request and restoring it on GPIO free. Signed-off-by: Prathamesh Shete Link: https://lore.kernel.org/20250305104939.15168-2-pshete@nvidia.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: tegra: Set SFIO mode to Mux Register

2025-04-10T12:39:20+00:00

[ Upstream commit 17013f0acb322e5052ff9b9d0fab0ab5a4bfd828 ] Tegra devices have an 'sfsel' bit field that determines whether a pin operates in SFIO (Special Function I/O) or GPIO mode. Currently, tegra_pinctrl_gpio_disable_free() sets this bit when releasing a GPIO. However, tegra_pinctrl_set_mux() can be called independently in certain code paths where gpio_disable_free() is not invoked. In such cases, failing to set the SFIO mode could lead to incorrect pin configurations, resulting in functional issues for peripherals relying on SFIO. This patch ensures that whenever set_mux() is called, the SFIO mode is correctly set in the Mux Register if the 'sfsel' bit is present. This prevents situations where the pin remains in GPIO mode despite being configured for SFIO use. Fixes: 971dac7123c7 ("pinctrl: add a driver for NVIDIA Tegra") Signed-off-by: Prathamesh Shete Link: https://lore.kernel.org/20250306050542.16335-1-pshete@nvidia.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: tegra: Use scope based of_node_put() cleanups

2024-06-26T09:55:34+00:00

Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan Acked-by: Thierry Reding Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-2-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij

phy: constify of_phandle_args in xlate

2024-02-23T12:13:14+00:00

The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Signed-off-by: Krzysztof Kozlowski Acked-by: Thierry Reding Acked-by: Linus Walleij Acked-by: Florian Fainelli #Broadcom Link: https://lore.kernel.org/r/20240217093937.58234-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul

pinctrl: tegra: Display pin function in pinconf-groups

2023-11-13T13:57:22+00:00

The function that a pin is muxed to can be read from the top-level pinctrl-maps debugfs file. However, this only reflects the values that were specified in device tree, so they will only show deviations from the hardware default setting. Display the current pinmux setting in the per-controller pinconf-groups debugfs file along with the rest of the per-pin configuration settings. Signed-off-by: Thierry Reding Tested-by: Luca Ceresoli Link: https://lore.kernel.org/r/20230929122101.466266-1-thierry.reding@gmail.com Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2023-11-04T05:15:19+00:00

Pull pin control updates from Linus Walleij: "No pin control core changes this time. New drivers: - Realtek RTD family pin control driver and RTD1619B, RTD1319D and RTD1315E subdrivers - Nuvoton NPCM8xx combined pin control and GPIO driver - Amlogic T7 pin control driver - Renesas RZ/G3S pin control driver Improvements: - A number of additional UART groups added to the Mediatek MT7981 driver - MPM pin maps added for Qualcomm MSM8996, SM6115, SM6125 and SDM660 - Extra GPIO banks for the Sunxi H616 - MLSP I2C6 function support in Qualcomm MSM8226 - Some __counted_by() annotations for dynamic arrays - Ongoing work to make remove() return void - LSBC groups and functions in the Renesas R8A7778" * tag 'pinctrl-v6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits) pinctrl: Use device_get_match_data() dt-bindings: pinctrl: qcom,sa8775p-tlmm: add missing wakeup-parent dt-bindings: pinctrl: nuvoton,npcm845: Add missing additionalProperties on gpio child nodes dt-bindings: pinctrl: brcm: Ensure all child node properties are documented pinctrl: renesas: rzn1: Convert to platform remove callback returning void pinctrl: renesas: rzg2l: Add RZ/G3S support dt-bindings: pinctrl: renesas: Document RZ/G3S SoC pinctrl: renesas: rzg2l: Add support for different DS values on different groups pinctrl: renesas: rzg2l: Move DS and OI to SoC-specific configuration pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets pinctrl: renesas: rzg2l: Index all registers based on port offset pinctrl: renesas: rzg2l: Add validation of GPIO pin in rzg2l_gpio_request() pinctrl: renesas: r8a7778: Add LBSC pins, groups, and functions pinctrl: intel: fetch community only when we need it pinctrl: cherryview: reduce scope of PIN_CONFIG_BIAS_HIGH_IMPEDANCE case pinctrl: cherryview: Convert to platform remove callback returning void pinctrl: sprd-sc9860: Convert to platform remove callback returning void pinctrl: qcom/msm: Convert to platform remove callback returning void pinctrl: qcom/lpi: Convert to platform remove callback returning void ...

pinctrl: tegra: add OF node when logging OF parsing errors

2023-09-27T08:54:59+00:00

These errors are not quite clear without also logging they device tree node being parsed, especially when the pinmux node has lots of subnodes. Adding the node name helps a lot in finding the node that triggers the error. Signed-off-by: Luca Ceresoli Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230926103938.334055-1-luca.ceresoli@bootlin.com Signed-off-by: Linus Walleij

Revert "pinctrl: tegra: Add support to display pin function"

2023-09-27T08:51:57+00:00

This reverts commit d1cd5b51bc9152dc2b63c5f843590272d6694d50. It was reported that some I2C3 functions stop working after this patch, and it is just debug help so let's revert it and investigate. Link: https://lore.kernel.org/linux-gpio/20230925183049.10a40546@booty/ Signed-off-by: Linus Walleij

Merge tag 'intel-pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

2023-08-25T13:47:18+00:00

intel-pinctrl for v6.6-1 * New library driver for Intel MID to deduplicate code (Raag Jadav) * Reuse common functions from pinctrl-intel to reduce the code (Raag Jadav) * Move most of the exported functions to the PINCTRL_INTEL namespace * Make use of pm_ptr() in Bay Trail and Lynxpoint drivers * Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper and use it in a few drivers * Consolidata ACPI dependency in Kconfig (Raag Jadav) * Fix address_space_handler() argument in Cherryview driver (Raag Jadav) * Optinmize byt_pin_config_set() to avoid IO in error cases (Raag Jadav) The following is an automated git shortlog grouped by driver: at91: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper baytrail: - Make use of pm_ptr() - reuse common functions from pinctrl-intel - consolidate common mask operation cherryview: - fix address_space_handler() argument - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper - reuse common functions from pinctrl-intel intel: - consolidate ACPI dependency - Switch to use exported namespace - export common pinctrl functions lynxpoint: - Make use of pm_ptr() - reuse common functions from pinctrl-intel Merge patch series: - Merge patch series "Introduce Intel Tangier pinctrl driver" - Merge patch series "Reuse common functions from pinctrl-intel" merrifield: - Adapt to Intel Tangier driver moorefield: - Adapt to Intel Tangier driver mvebu: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pm: - Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper renesas: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper tangier: - Introduce Intel Tangier driver tegra: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper Signed-off-by: Linus Walleij