kernel/linux.git/drivers/pinctrl/sunxi, branch v5.15.7

Merge tag 'irq-core-2021-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2021-08-30T21:38:37+00:00

Pull irq updates from Thomas Gleixner: "Updates to the interrupt core and driver subsystems: Core changes: - The usual set of small fixes and improvements all over the place, but nothing stands out MSI changes: - Further consolidation of the PCI/MSI interrupt chip code - Make MSI sysfs code independent of PCI/MSI and expose the MSI interrupts of platform devices in the same way as PCI exposes them. Driver changes: - Support for ARM GICv3 EPPI partitions - Treewide conversion to generic_handle_domain_irq() for all chained interrupt controllers - Conversion to bitmap_zalloc() throughout the irq chip drivers - The usual set of small fixes and improvements" * tag 'irq-core-2021-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (57 commits) platform-msi: Add ABI to show msi_irqs of platform devices genirq/msi: Move MSI sysfs handling from PCI to MSI core genirq/cpuhotplug: Demote debug printk to KERN_DEBUG irqchip/qcom-pdc: Trim unused levels of the interrupt hierarchy irqdomain: Export irq_domain_disconnect_hierarchy() irqchip/gic-v3: Fix priority comparison when non-secure priorities are used irqchip/apple-aic: Fix irq_disable from within irq handlers pinctrl/rockchip: drop the gpio related codes gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type gpio/rockchip: support next version gpio controller gpio/rockchip: use struct rockchip_gpio_regs for gpio controller gpio/rockchip: add driver for rockchip gpio dt-bindings: gpio: change items restriction of clock for rockchip,gpio-bank pinctrl/rockchip: add pinctrl device to gpio bank struct pinctrl/rockchip: separate struct rockchip_pin_bank to a head file pinctrl/rockchip: always enable clock for gpio controller genirq: Fix kernel doc indentation EDAC/altera: Convert to generic_handle_domain_irq() powerpc: Bulk conversion to generic_handle_domain_irq() nios2: Bulk conversion to generic_handle_domain_irq() ...

pinctrl: Bulk conversion to generic_handle_domain_irq()

2021-08-12T10:39:39+00:00

Wherever possible, replace constructs that match either generic_handle_irq(irq_find_mapping()) or generic_handle_irq(irq_linear_revmap()) to a single call to generic_handle_domain_irq(). Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Signed-off-by: Marc Zyngier

pinctrl: sunxi: Don't underestimate number of functions

2021-08-10T12:55:35+00:00

When we are building all the various pinctrl structures for the Allwinner pinctrl devices, we do some estimation about the maximum number of distinct function (names) that we will need. So far we take the number of pins as an upper bound, even though we can actually have up to four special functions per pin. This wasn't a problem until now, since we indeed have typically far more pins than functions, and most pins share common functions. However the H616 "-r" pin controller has only two pins, but four functions, so we run over the end of the array when we are looking for a matching function name in sunxi_pinctrl_add_function - there is no NULL sentinel left that would terminate the loop: [ 8.200648] Unable to handle kernel paging request at virtual address fffdff7efbefaff5 [ 8.209179] Mem abort info: .... [ 8.368456] Call trace: [ 8.370925] __pi_strcmp+0x90/0xf0 [ 8.374559] sun50i_h616_r_pinctrl_probe+0x1c/0x28 [ 8.379557] platform_probe+0x68/0xd8 Do an actual worst case allocation (4 functions per pin, three common functions and the sentinel) for the initial array allocation. This is now heavily overestimating the number of functions in the common case, but we will reallocate this array later with the actual number of functions, so it's only temporarily. Fixes: 561c1cf17c46 ("pinctrl: sunxi: Add support for the Allwinner H616-R pin controller") Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/20210722132548.22121-1-andre.przywara@arm.com Signed-off-by: Linus Walleij

pinctrl: sunxi: Add support for the Allwinner H616-R pin controller

2021-01-21T21:15:46+00:00

There are only two pins left now, used to connect to the PMIC via I2C. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20210118020848.11721-6-andre.przywara@arm.com Signed-off-by: Linus Walleij

pinctrl: sunxi: Add support for the Allwinner H616 pin controller

2021-01-21T21:14:18+00:00

Port A is used for an internal connection to some analogue circuitry which looks like an AC200 IP (as in the H6), though this is not mentioned in the manual. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/20210118020848.11721-5-andre.przywara@arm.com Signed-off-by: Linus Walleij

pinctrl: sunxi: h6-r: Add s_rsb pin functions

2021-01-06T20:10:04+00:00

As there is an RSB controller in the H6 SoC, there should be some pin configuration for it. While no such configuration is documented, the "s_i2c" pins are suspiciously on the "alternate" function 3, with no primary function 2 given. This suggests the primary function for these pins is actually RSB, and that is indeed the case. Add the "s_rsb" pin functions so the RSB controller can be used. Signed-off-by: Samuel Holland Acked-by: Chen-Yu Tsai Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/20210103100007.32867-3-samuel@sholland.org Signed-off-by: Linus Walleij

pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler

2020-11-24T08:41:29+00:00

It is found on many allwinner soc that there is a low probability that the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This will cause the interrupt status of a gpio bank to always be active on gic, preventing gic from responding to other spi interrupts correctly. So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler(). Signed-off-by: Yangtao Li Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/85263ce8b058e80cea25c6ad6383eb256ce96cc8.1604988979.git.frank@allwinnertech.com Signed-off-by: Linus Walleij

pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON

2020-11-24T08:40:54+00:00

The interrupt descriptor cannot be found in the interrupt processing function, and this situation cannot happen when the system is running normally. It doesn't seem right to return directly to the status of not handling gic. In this case, it must be a bug, let's mark it with WARN_ON. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/470ebae22fc5434ad5409c4f6e29255467b3cef6.1604988979.git.frank@allwinnertech.com Signed-off-by: Linus Walleij

pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller

2020-11-24T08:40:03+00:00

A100's pin starts with PB, so it should start with 1. Fixes: 473436e7647d6 ("pinctrl: sunxi: add support for the Allwinner A100 pin controller") Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/9db51667bf9065be55beafd56e5c319e3bbe8310.1604988979.git.frank@allwinnertech.com Signed-off-by: Linus Walleij

pinctrl: sunxi: add support for the Allwinner A100 pin controller

2020-09-12T10:35:42+00:00

This commit introduces support for the pin controller on A100. Signed-off-by: Yangtao Li Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/4e331a2ed4a30c883df6157bc5c52bb686aa8e0d.1595572867.git.frank@allwinnertech.com Signed-off-by: Linus Walleij