kernel/linux.git/drivers/pinctrl/sunxi, branch v4.17.1

pinctrl: sunxi: add support for the Allwinner H6 main pin controller

2018-03-27T13:09:42+00:00

The Allwinner H6 SoC has two pin controllers, one main controller (called CPUX-PORT in user manual) and one controller in CPUs power domain (called CPUS-PORT in user manual). This commit introduces support for the main pin controller on H6. The pin bank A and B are not wired out and hidden from the SoC's documents, however it's shown that the "ATE" (an AC200 chip co-packaged with the H6 die) is connected to the main SoC die via these pin banks. The information about these banks is just copied from the BSP pinctrl driver, but re-formatted to fit the mainline pinctrl driver format. The GPIO functions are dropped, as they're impossible to use -- except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring Reviewed-by: Andre Przywara Acked-by: Maxime Ripard Signed-off-by: Linus Walleij

pinctrl: sunxi: change irq_bank_base to irq_bank_map

2018-03-27T13:07:49+00:00

The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Signed-off-by: Linus Walleij

pinctrl: sunxi: introduce IRQ bank conversion function

2018-03-27T13:06:25+00:00

The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Some refactors in the sunxi pinctrl framework are needed. This commit introduces a IRQ bank conversion function, which replaces the "(bank_base + bank)" code in IRQ register access. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Signed-off-by: Linus Walleij

pinctrl: sunxi: refactor irq related register function to have desc

2018-03-27T13:04:10+00:00

As the new H6 SoC has holes in the IRQ registers, refactor the IRQ related register function for getting the full pinctrl desc structure. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Signed-off-by: Linus Walleij

pinctrl: sunxi: always look for apb block

2018-03-23T02:43:48+00:00

The Allwinner pinctrl device tree binding suggests that a clock named "apb" would drive the pin controller IP. However (for legacy reasons) we rely on this clock actually being the first clock defined. Since named clocks can be in any order, let's explicitly check for a clock called "apb" if there is more than one clock referenced. Kudo to Maxime for suggesting this much more elegant approach. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2018-02-02T22:22:53+00:00

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.16 kernel cycle. Like with GPIO it is actually a bit calm this time. Core changes: - After lengthy discussions and partly due to my ignorance, we have merged a patch making pinctrl_force_default() and pinctrl_force_sleep() reprogram the states into the hardware of any hogged pins, even if they are already in the desired state. This only apply to hogged pins since groups of pins owned by drivers need to be managed by each driver, lest they could not do things like runtime PM and put pins to sleeping state even if the system as a whole is not in sleep. New drivers: - New driver for the Microsemi Ocelot SoC. This is used in ethernet switches. - The X-Powers AXP209 GPIO driver was extended to also deal with pin control and moved over from the GPIO subsystem. This circuit is a mixed-mode integrated circuit which is part of AllWinner designs. - New subdriver for the Qualcomm MSM8998 SoC, core of a high end mobile devices (phones) chipset. - New subdriver for the ST Microelectronics STM32MP157 MPU and STM32F769 MCU from the STM32 family. - New subdriver for the MediaTek MT7622 SoC. This is used for routers, repeater, gateways and such network infrastructure. - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC has multimedia features and target "smart devices", I guess in-car entertainment, in-flight entertainment, industrial control panels etc. General improvements: - Incremental improvements on the SH-PFC subdrivers for things like the CAN bus. - Enable the glitch filter on Baytrail GPIOs used for interrupts. - Proper handling of pins to GPIO ranges on the Semtec SX150X - An IRQ setup ordering fix on MCP23S08. - A good set of janitorial coding style fixes" * tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits) pinctrl: mcp23s08: fix irq setup order pinctrl: Forward declare struct device pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding pinctrl: stm32: add STM32F769 MCU support pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping pinctrl: sx150x: Register pinctrl before adding the gpiochip pinctrl: sx150x: Unregister the pinctrl on release pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe() pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show() pinctrl: pinmux: Use seq_putc() in pinmux_pins_show() pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show() pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call pinctrl: mediatek: mt7622: fix potential uninitialized value being returned pinctrl: uniphier: refactor drive strength get/set functions pinctrl: imx7ulp: constify struct imx_cfg_params_decode pinctrl: imx: constify struct imx_pinctrl_soc_info pinctrl: imx7d: simplify imx7d_pinctrl_probe pinctrl: imx: use struct imx_pinctrl_soc_info as a const pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly. pinctrl: qcom: Add msm8998 pinctrl driver ...

pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding

2018-01-22T08:55:05+00:00

Signed-off-by: Geert Uytterhoeven Signed-off-by: Linus Walleij

pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly.

2018-01-10T13:44:20+00:00

Pin function can not be match correctly when SUNXI_PIN describe with mutiple variant and same function. such as: on pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_VARIANT(0x2, "pwm", /* PWM0 */ PINCTRL_SUN4I_A10 | PINCTRL_SUN7I_A20), SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM0 */ PINCTRL_SUN8I_R40)), it would always match to the first variant function (PINCTRL_SUN4I_A10, PINCTRL_SUN7I_A20) so we should add variant compare on it. Signed-off-by: hao_zhang Acked-by: Maxime Ripard Signed-off-by: Linus Walleij

pinctrl: sunxi: fix a typo when merging A20 support to A10 driver

2017-12-28T14:06:01+00:00

When merging A20 pinctrl support to A10 pinctrl driver, the I2C function of PI3 is wrongly written as "i2c3" (it should be "i2c4"). Fix this typo. Fixes: cad4e209c102 ("pinctrl: sunxi: add support of R40 to A10 pinctrl driver") Reported-by: Mark Kettenis Signed-off-by: Icenowy Zheng Signed-off-by: Linus Walleij

pinctrl: sunxi: Disable strict mode for H5 driver

2017-11-30T15:50:43+00:00

All of the H5 boards in the kernel reference the MMC0 CD pin twice in their DT, so strict mode will make the MMC driver fail to load. To keep existing DTs working, disable strict mode in the H5 driver. Signed-off-by: Andre Przywara Reported-by: Chris Obbard Acked-by: Maxime Ripard Signed-off-by: Linus Walleij