Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v6.19.11 2025-10-13T01:02:21+00:00 2025-10-13T01:02:21+00:00 SeonGu Kang ksk4725@coasia.com 2025-09-17T07:00:04+00:00 urn:sha1:3cfc60e09bdc95483875f0b63cfdc23aea67135b Add Axis ARTPEC-9 SoC specific configuration data to enable pinctrl. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 2025-10-13T00:20:57+00:00 Ivaylo Ivanov ivo.ivanov.ivanov1@gmail.com 2025-09-14T11:44:57+00:00 urn:sha1:5b6b7d39cee69373dc61ca22164d616e4faf60c6 Add support for the pin-controller found on the exynos8890 SoC, used in Samsung Galaxy S7. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 2025-09-02T10:30:22+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2025-08-30T11:16:58+00:00 urn:sha1:358253fa8179ab4217ac283b56adde0174186f87 Drop unused declarations after S3C24xx SoC family removal in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"). Fixes: 1ea35b355722 ("ARM: s3c: remove s3c24xx specific hacks") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250830111657.126190-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 2025-09-01T06:32:02+00:00 SeonGu Kang ksk4725@coasia.com 2025-09-01T05:19:22+00:00 urn:sha1:d4ac729964d8967261fe15fdc8f249729f923120 Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250901051926.59970-3-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 2025-08-07T08:07:06+00:00 Bartosz Golaszewski bartosz.golaszewski@linaro.org 2025-07-17T13:21:26+00:00 urn:sha1:d9d87d90cc0b10cd56ae353f50b11417e7d21712 The conversion of all GPIO drivers to using the .set_rv() and .set_multiple_rv() callbacks from struct gpio_chip (which - unlike their predecessors - return an integer and allow the controller drivers to indicate failures to users) is now complete and the legacy ones have been removed. Rename the new callbacks back to their original names in one sweeping change. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> 2025-07-05T07:35:22+00:00 Peter Griffin peter.griffin@linaro.org 2025-07-02T12:15:24+00:00 urn:sha1:683d532dfc9657ab8aae25204f378352ed144646 When adding the dedicated gs101_wkup_irq_chip struct to support the eint wakeup mask the .eint_con, eint_mask and .eint_pend fields were missed. The result is that irqs on gs101 for the buttons etc are broken. Reported-by: André Draszik <andre.draszik@linaro.org> Fixes: 2642f55d44ce ("pinctrl: samsung: add support for gs101 wakeup mask programming") Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250702-fix-gs101-irqchip-v1-1-ccc84b44ad72@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 2025-06-25T14:17:05+00:00 Peter Griffin peter.griffin@linaro.org 2025-06-19T11:18:16+00:00 urn:sha1:2642f55d44ce563f227dd9c620eda0dec8d882be gs101 differs to other currently supported SoCs in that it has 3 wakeup mask registers for the 67 external wakeup interrupt pins in alive and far_alive. EINT_WAKEUP_MASK 0x3A80 EINT[31:0] EINT_WAKEUP_MASK2 0x3A84 EINT[63:32] EINT_WAKEUP_MASK3 0x3A88 EINT[66:64] Add gs101 specific callbacks and a dedicated gs101_wkup_irq_chip struct to handle these differences. The current wakeup mask with upstream is programmed as WAKEUP_MASK0[0x3A80] value[0xFFFFFFFF] WAKEUP_MASK1[0x3A84] value[0xF2FFEFFF] WAKEUP_MASK2[0x3A88] value[0xFFFFFFFF] Which corresponds to the following wakeup sources: gpa7-3 vol down gpa8-1 vol up gpa10-1 power gpa8-2 typec-int Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250619-gs101-eint-mask-v1-2-89438cfd7499@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 2025-06-25T14:17:05+00:00 Peter Griffin peter.griffin@linaro.org 2025-06-19T11:18:15+00:00 urn:sha1:c8edb80494407f65a253ea63ffbae3fb831f397a To avoid having an exact copy of this struct for gs101 rename it and use it for both SoCs for eint banks. The purpose of this for exynosautov920 and gs101 is to obtain the PMU syscon for writing the calculated WAKEUP_MASK register(s). Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250619-gs101-eint-mask-v1-1-89438cfd7499@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 2025-05-13T22:01:56+00:00 Linus Walleij linus.walleij@linaro.org 2025-05-13T22:01:56+00:00 urn:sha1:86ea0b826fb26d3579f2fe5a68e44e5ac17f3301 Samsung pinctrl drivers changes for v6.16 Refactor the driver suspend and resume to handle Google GS101 EINT GPIO pin banks and add the alive pin bank for that SoC. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2025-04-29T08:34:46+00:00 Bartosz Golaszewski bartosz.golaszewski@linaro.org 2025-04-24T08:35:35+00:00 urn:sha1:9e4c444755b1525e9cb0798ca2dccbb18b0c0393 struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250424-gpiochip-set-rv-pinctrl-part2-v1-12-504f91120b99@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>