kernel/linux.git/drivers/pinctrl/qcom, branch v7.2-rc1

Merge tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2026-06-18T22:03:21+00:00

Pull pin control updates from Linus Walleij: "Core changes: - Add new generic callbacks to populate per-pin pin controllers creating groups and functions from the device tree building out pinctrl_generic_to_map() and move the Spacemit driver over to use this - Generic board-level pin control driver using the mux framework New pin controller drivers: - Amlogic (meson) A9 SoC - Aspeed AST2700 SoC0 and SoC1 - nVidia Tegra264 and Tegra238 - Qualcomm Nord TLMM, Shikra TLMM, SM6350 LPASS LPI, and IPQ9650 TLMM - Renesas RZ/G3L SoC - UltraRISC DP1000 Improvements: - Handle pull up/pull down properly in the Renesas RZG2L driver - Fix up nVidia Tegra 234 DT bindings - Fix up pin definitions in the Qualcomm Eliza driver - Qualcomm PM8010 GPIO support in the PM8010 - Qualcomm SM6115 EGPIO support in the SM6115 - Switch Qualcomm LPASS LPI drivers to use runtime PM for power management - Clean up the Qualcomm Kconfig business a bit to include the necessary drivers for each subarch - Fix output glitch in the Amlogic (meson) A4 pin controller - Move the Airoha driver from the Mediatek directory to its own directory. It is too different from other Mediatek hardware - A slew of fixes to the Airoha AN7581 and AN7583 drivers" * tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (151 commits) pinctrl: Export pinctrl_get_group_selector() pinctrl: Match DT helper types pinctrl: qcom: Register functions before enabling pinctrl pinctrl: meson: amlogic-a4: use nolock get range pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl controller pinctrl: qcom: Remove unused macro definitions pinctrl: tegra: PINCTRL_TEGRA264 should depend on ARCH_TEGRA pinctrl: tegra: PINCTRL_TEGRA238 should depend on ARCH_TEGRA pinctrl: tegra238: add missing AON pin groups dt-bindings: pinctrl: tegra238: add missing AON pin groups pinctrl: airoha: an7583: remove undefined groups from pcm_spi pin function pinctrl: airoha: an7583: fix phy1_led1 pin function pinctrl: airoha: an7583: add missed gpio22 pin group pinctrl: airoha: an7583: fix gpio21 pin group pinctrl: airoha: fix pwm pin function for an7581 and an7583 pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin function pinctrl: airoha: an7581: fix incorrect led mapping in phy4_led1 pin function pinctrl: airoha: an7583: fix misprint in gpio19 pinconf pinctrl: airoha: an7581: fix misprint in gpio19 pinconf ...

pinctrl: qcom: Register functions before enabling pinctrl

2026-06-11T13:03:02+00:00

pinctrl consumers can request states while the pinctrl core enables the controller. On Qualcomm pinctrl drivers this can happen before the SoC function list has been registered, which leaves the function table incomplete during state lookup. On APQ8064 this can fail while claiming pinctrl hogs: apq8064-pinctrl 800000.pinctrl: invalid function ps_hold in map table apq8064-pinctrl 800000.pinctrl: error claiming hogs: -22 apq8064-pinctrl 800000.pinctrl: could not claim hogs: -22 Register Qualcomm pinctrl with devm_pinctrl_register_and_init(), add the SoC pin functions, and only then enable the pinctrl device. Signed-off-by: Alexandre MINETTE Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij

pinctrl: qcom: Remove unused macro definitions

2026-06-11T12:06:47+00:00

The macros QUP_I3C and UFS_RESET are defined in some platforms and yet not used. Remove these macros as they are unnecessary. Signed-off-by: Navya Malempati Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij

pinctrl: qcom: eliza: Add missing sdc2 pin function mappings

2026-06-10T21:29:48+00:00

GPIOs 38, 39, 48 and 49 support the SDC2 DATA function, while GPIO 51 supports SDC2 CMD and GPIO 62 supports SDC2 CLK. However, the sdc2 pin function is not listed in the corresponding pingroup definitions, preventing these pins from being muxed for SDC2 operation. Add the missing sdc2 function mappings. Fixes: 6f26989e15fb ("pinctrl: qcom: Add Eliza pinctrl driver") Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij

pinctrl: qcom: lpass-lpi: drop unused runtime-PM write helper

2026-06-10T20:37:56+00:00

lpi_gpio_write() became unused after the PM clock runtime conversion switched write paths to register helper calls inside callers that already hold an active runtime-PM reference. With -Werror this triggers: error: 'lpi_gpio_write' defined but not used [-Wunused-function] Drop the dead wrapper and rename the low-level MMIO helpers from __lpi_gpio_* to lpi_gpio_*_reg for neutral register-accessor naming. Fixes: b719ede389d8 ("pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PM") Reported-by: Nathan Chancellor Closes: https://lore.kernel.org/all/f03850f6-186d-4988-a450-e6e95f24a551@kernel.org/ Signed-off-by: Ajay Kumar Nandam Signed-off-by: Linus Walleij

pinctrl: qcom: Fix resolving register base address from device node

2026-06-08T19:30:53+00:00

Commit 56ffb63749f4 ("pinctrl: qcom: add multi TLMM region option parameter") added reg-names property based register reading. However multiple platforms are not using the reg-names as they have only single TLMM register region. Commit tried to handle this using the default_region module parameter, however this condition is unreachable as the error return precedes it by just checking if reg-names property exists or not, making it impossible to use tlmm-test for the SoCs (x1e80100) which don't have reg-names property in TLMM device. Fix this by moving the default_region check at the start of the tlmm_reg_base(). Fixes: 56ffb63749f4 ("pinctrl: qcom: add multi TLMM region option parameter") Signed-off-by: Sneh Mankad Reviewed-by: Dmitry Baryshkov Signed-off-by: Linus Walleij

pinctrl: qcom: Modify MSM_PULL_MASK to accurately represent PULL bits

2026-06-08T19:30:46+00:00

MSM_PULL_MASK currently spans bits [2:0], but the GPIO_PULL field in the GPIO_CFG register only occupies bits [1:0]. Bit 2 belongs to FUNC_SEL. MSM_PULL_MASK is used to isolate the GPIO_PULL bits before writing the pull configuration (PULL_DOWN: 0x1, PULL_UP: 0x3) to the GPIO_CFG register. Narrow it to bits [1:0] to prevent unintended modification of the FUNC_SEL field. This causes no functional change since the driver currently does not modify the FUNC_SEL bit, but align the mask with hardware configuration nonetheless. Signed-off-by: Sneh Mankad Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij

pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PM

2026-06-08T08:46:42+00:00

Convert the LPASS LPI pinctrl driver to use the PM clock framework for runtime power management. This allows the LPASS LPI pinctrl driver to drop clock votes when idle, improves power efficiency on platforms using LPASS LPI island mode, and aligns the driver with common runtime PM patterns used across Qualcomm LPASS subsystems. Guard GPIO register read/write helpers and slew-rate register programming with synchronous runtime PM calls so the device is active during MMIO operations whenever autosuspend is enabled. Make PINCTRL_LPASS_LPI depend on PM_CLK, since this patch introduces direct PM clock API use in the shared core. Suggested-by: Konrad Dybcio Signed-off-by: Ajay Kumar Nandam Signed-off-by: Linus Walleij

pinctrl: qcom: lpass-lpi: Enable runtime PM hooks on LPASS LPI SoCs

2026-06-08T08:46:41+00:00

The LPASS LPI core conversion to PM clock framework relies on variant drivers wiring runtime PM callbacks. Hook up runtime PM callbacks for the LPASS LPI variant drivers touched in this patch so they are prepared for the shared core conversion. This commit is a preparatory NOP on its own, as runtime PM is still disabled on these devices until the following core conversion patch. This is a mechanical per-variant driver update that relies on the same generic PM clock flow (of_pm_clk_add_clks() + pm_clk_suspend/ pm_clk_resume()) and DT-provided clocks. Runtime behavior was validated on Kodiak (sc7280). Suggested-by: Konrad Dybcio Signed-off-by: Ajay Kumar Nandam Signed-off-by: Linus Walleij

pinctrl: qcom: Replace open coded eoi call with irq_chip_eoi_parent()

2026-05-29T20:35:14+00:00

Before commit 14dbe186b9d4 ("pinctrl: msmgpio: Make the irqchip immutable") msm gpio irqchip conditionally initialized pctrl->irq_chip.irq_eoi to irq_chip_eoi_parent() only for the GPIO irqs having a wakeup capable irq. In order to make gpio irqchip immutable pctrl->irq_chip.irq_eoi is initialized to msm_gpio_irq_eoi() which now gets invoked for both wake up and non-wakeup capable GPIO IRQs. Replace open coded eoi call to parent irqchip with irq_chip_eoi_parent(). Since the irq_chip_*_parent() APIs internally do not check the valid parent data is present to ensure irq_chip_eoi_parent() is only invoked for wakeup capable GPIOs validate d->parent_data within msm_gpio_irq_eoi(). For non wakeup capable GPIOs d->parent_data will be NULL since parent irqchip diconnects hierarchy using irq_domain_disconnect_hierarchy() and later irq framework trims hierarchy using irq_domain_trim_hierarchy() which makes d->parent_data as NULL. No functional impact. Reviewed-by: Bjorn Andersson Signed-off-by: Maulik Shah Reviewed-by: Dmitry Baryshkov Signed-off-by: Linus Walleij