kernel/linux.git/drivers/pinctrl/qcom, branch v4.11.5

pinctrl: qcom: ipq4019: add missing pingroups for pins > 70

2017-03-23T09:13:15+00:00

This patch adds the missing PINGROUP for GPIO70-99. This fixes a crash that happens in pinctrl-msm, if any of the GPIO70-99 are accessed. Fixes: 5303f7827fcd41d ("pinctrl: qcom: ipq4019: set ngpios to correct value") Signed-off-by: Christian Lamparter Acked-by: Bjorn Andersson Signed-off-by: Linus Walleij

pinctrl: qcom: Don't clear status bit on irq_unmask

2017-03-23T09:10:39+00:00

Clearing the status bit on irq_unmask will discard any pending interrupt that did arrive after the irq_ack, i.e. while the IRQ handler function was executing. Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver") Cc: stable@vger.kernel.org Cc: Stephen Boyd Reported-by: Timur Tabi Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij

pinctrl: qcom: add get_direction function

2017-03-06T13:38:05+00:00

The get_direction callback function allows gpiolib to know the current direction (input vs output) for a given GPIO. This is particularly useful on ACPI systems, where the GPIOs are configured only by firmware (typically UEFI), so the only way to know the initial values to query the hardware directly. Without this function, gpiolib thinks that all GPIOs are configured for input. Signed-off-by: Timur Tabi Signed-off-by: Linus Walleij

pinctrl: qcom: Use raw spinlock variants

2017-01-26T10:06:15+00:00

The MSM pinctrl driver currently implements an irq_chip for handling GPIO interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. On real-time kernels, this fixes an OOPs which looks like the following, as reported by Brian Wrenn: kernel BUG at kernel/locking/rtmutex.c:1014! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP Modules linked in: spidev_irq(O) smsc75xx wcn36xx [last unloaded: spidev] CPU: 0 PID: 1163 Comm: irq/144-mmc0 Tainted: G W O 4.4.9-linaro-lt-qcom #1 PC is at rt_spin_lock_slowlock+0x80/0x2d8 LR is at rt_spin_lock_slowlock+0x68/0x2d8 [..] Call trace: rt_spin_lock_slowlock rt_spin_lock msm_gpio_irq_ack handle_edge_irq generic_handle_irq msm_gpio_irq_handler generic_handle_irq __handle_domain_irq gic_handle_irq Reported-by: Brian Wrenn Tested-by: Brian Wrenn Signed-off-by: Julia Cartwright Acked-by: Bjorn Andersson Signed-off-by: Linus Walleij

pinctrl: qcom: msm8660: rename some SDC1->SDC4

2017-01-03T08:26:20+00:00

These four pins are for SDC4, not SDC1. They are grouped for SDC4 later in the file so this must be a typo. Reviewed-by: Björn Andersson Signed-off-by: Linus Walleij

pinctrl: qcom: Add msm8994 pinctrl driver

2016-11-04T22:55:36+00:00

Initial pinctrl driver for QCOM msm8994 platforms. In order to continue the initial board support for QCOM msm8994/msm8992 presented in patches from Jeremy McNicoll , let's put a proper pinctrl driver in place. Currently, the DT for these platforms uses the msm8x74 pinctrl driver to enable basic UART. Beyond the first few pins the rest are different enough to justify it's own driver. Note: This driver is also used by QCOM's msm8992 platform as it's TLM block is the same. - Initial formatting and style was taken from the msm8x74 pinctrl driver added by Björn Andersson - Data was then adjusted per QCOM MSM8994v2 documentation for Top Level Multiplexing - Bindings documentation was based on qcom,msm8996-pinctrl.txt by Joonwoo Park and then modified for msm8994 content Signed-off-by: Michael Scott Tested-by: Jeremy McNicoll Acked-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Linus Walleij

pinctrl: qcom: fix masking of pinmux functions

2016-10-03T22:36:20+00:00

The following commit introduced a regression by not properly masking the calculated value. Fixes: 47a01ee9a6c3 ("pinctrl: qcom: Clear all function selection bits") Signed-off-by: John Crispin Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Signed-off-by: Linus Walleij

pinctrl: qcom: Add generic ssbi and spmi GPIO/MPP bindings

2016-08-11T08:18:46+00:00

The drivers don't really need to know which PMIC they're for, so make a generic binding for them. This alleviates us from updating the drivers every time a new PMIC comes out. It's still recommended that we update the binding with new PMIC models and always specify the specific model for the MPPs and gpios before the generic compatible string in devicetree, but this at least cuts down on adding more and more compatible strings to the drivers until we actually need them. Cc: Acked-by: "Ivan T. Ivanov" Reviewed-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Stephen Boyd Signed-off-by: Linus Walleij

pinctrl: qcom: establish proper EBI2 pin groups

2016-07-08T17:37:33+00:00

After some digging around I found documentation (!) of the APQ8060 EBI2 pin groups. It turns out I first need to split the group in two: ebi2cs and ebi2 proper. The chip select pins are kind of orthogonal to the other EBI2 pins since CS1B and CS2B can be muxed over address bits 7 and 6 (don't know why, but they can). This is good to fix up before we add users. Also found what the "holes" in the assignment all the way up to gpio158 was actually for. All mux documentation comes from "Snapdragon(TM) S3 APQ8060-based DragonBoard(TM) GPIO User Guide Rev. E August 10, 2012", published by Bsquare Corporation. As the documentation seems a bit hard to come by I put some comments in the group definitions so that it is clear to all readers what is going on here and what the lines are used for. Cc: Björn Andersson Cc: Stephen Boyd Reviewed-by: Andy Gross Signed-off-by: Linus Walleij

pinctrl: qcom: add support for EBI2

2016-07-03T21:35:05+00:00

Add support to mux in the second external bus interface as follows: - CS1 and CS2 on GPIO39 and GPIO40 as func 2 - ADDR_7 thru ADDR_0 on GPIO123 thru GPIO130 as func 1 - CS4, CS3 and CS0 on GPIO132, GPIO133, GPIO134 as func 1 - DATA_15 thru DATA_0 on GPIO135 thru GPIO150 as func 1 - OE on GPIO151 as func 1 - ADV on GPIO153 as func 1 - WE on GPIO157 as func 1 This external bus is used on the APQ8060 Dragonboard to connect an external SMSC9211 ethernet adapter, but there are many other usecases for the EBI2. Cc: Stephen Boyd Reviewed-by: Björn Andersson Signed-off-by: Linus Walleij