kernel/linux.git/drivers/pinctrl/qcom, branch linux-5.9.y

pinctrl: qcom: sm8250: Specify PDC map

2020-11-18T18:22:18+00:00

[ Upstream commit b41efeed507addecb92e83dd444d86c1fbe38ae0 ] Specify the PDC mapping for SM8250, so that gpio interrupts are propertly mapped to the wakeup IRQs of the PDC. Fixes: 4e3ec9e407ad ("pinctrl: qcom: Add sm8250 pinctrl driver.") Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201028043642.1141723-1-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback

2020-11-18T18:22:18+00:00

[ Upstream commit 71266d9d39366c9b24b866d811b3facaf837f13f ] When GPIOs that are routed to PDC are used as output they can still latch the IRQ pending at GIC. As a result the spurious IRQ was handled when the client driver change the direction to input to starts using it as IRQ. Currently such erroneous latched IRQ are cleared with .irq_enable callback however if the driver continue to use GPIO as interrupt and invokes disable_irq() followed by enable_irq() then everytime during enable_irq() previously latched interrupt gets cleared. This can make edge IRQs not seen after enable_irq() if they had arrived after the driver has invoked disable_irq() and were pending at GIC. Move clearing erroneous IRQ to .irq_request_resources callback as this is the place where GPIO direction is changed as input and its locked as IRQ. While at this add a missing check to invoke msm_gpio_irq_clear_unmask() from .irq_enable callback only when GPIO is not routed to PDC. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah Link: https://lore.kernel.org/r/1604561884-10166-1-git-send-email-mkshah@codeaurora.org Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: qcom: Use return value from irq_set_wake() call

2020-10-29T09:11:02+00:00

[ Upstream commit f41aaca593377a4fe3984459fd4539481263b4cd ] msmgpio irqchip was not using return value of irq_set_irq_wake() callback since previously GIC-v3 irqchip neither had IRQCHIP_SKIP_SET_WAKE flag nor it implemented .irq_set_wake callback. This lead to irq_set_irq_wake() return error -ENXIO. However from 'commit 4110b5cbb014 ("irqchip/gic-v3: Allow interrupt to be configured as wake-up sources")' GIC irqchip has IRQCHIP_SKIP_SET_WAKE flag. Use return value from irq_set_irq_wake() and irq_chip_set_wake_parent() instead of always returning success. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah Signed-off-by: Marc Zyngier Tested-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Acked-by: Bjorn Andersson Acked-by: Linus Walleij Link: https://lore.kernel.org/r/1601267524-20199-3-git-send-email-mkshah@codeaurora.org Signed-off-by: Sasha Levin

pinctrl: qcom: Set IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags

2020-10-29T09:11:02+00:00

[ Upstream commit c5f72aeb659eb2f809b9531d759651514d42aa3a ] Both IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags are already set for msmgpio's parent PDC irqchip but GPIO interrupts do not get masked during suspend or during setting irq type since genirq checks irqchip flag of msmgpio irqchip which forwards these calls to its parent PDC irqchip. Add irqchip specific flags for msmgpio irqchip to mask non wakeirqs during suspend and mask before setting irq type. Masking before changing type make sures any spurious interrupt is not detected during this operation. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah Signed-off-by: Marc Zyngier Tested-by: Stephen Boyd Reviewed-by: Douglas Anderson Acked-by: Bjorn Andersson Acked-by: Linus Walleij Link: https://lore.kernel.org/r/1601267524-20199-2-git-send-email-mkshah@codeaurora.org Signed-off-by: Sasha Levin

pinctrl: qcom: sm8250: correct sdc2_clk

2020-10-01T07:51:16+00:00

Correct sdc2_clk pin definition (register offset is wrong, verified by the msm-4.19 driver). Fixes: 4e3ec9e407ad ("pinctrl: qcom: Add sm8250 pinctrl driver.") Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200914091846.55204-1-dmitry.baryshkov@linaro.org Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2020-08-09T19:52:28+00:00

Pull pin control updates from Linus Walleij: "This is the bulk of the pin control changes for the v5.9 kernel series: Core changes: - The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range() macro" was put in an immutable branch and merged into the pinctrl tree as well. We see these changes also here. - Improved debug output for pins used as GPIO. New drivers: - Ocelot Sparx5 SoC driver. - Intel Emmitsburg SoC subdriver. - Intel Tiger Lake-H SoC subdriver. - Qualcomm PM660 SoC subdriver. - Renesas SH-PFC R8A774E1 subdriver. Driver improvements: - Linear improvement and cleanups of the Intel drivers for Cherryview, Lynxpoint, Baytrail etc. Improved locking among other things. - Renesas SH-PFC has added support for RPC pins, groups, and functions to r8a77970 and r8a77980. - The newere Freescale (now NXP) i.MX8 pin controllers have been modularized. This is driven by the Google Android GKI initiative I think. - Open drain support for pins on the Qualcomm IPQ4019. - The Ingenic driver can handle both edges IRQ detection. - A big slew of documentation fixes all over the place. - A few irqchip template conversions by yours truly. * tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits) dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC pinctrl: stmfx: Use irqchip template pinctrl: amd: Use irqchip template pinctrl: mediatek: fix build for tristate changes pinctrl: samsung: Use bank name as irqchip name pinctrl: core: print gpio in pins debugfs file pinctrl: mediatek: add mt6779 eint support pinctrl: mediatek: add pinctrl support for MT6779 SoC pinctrl: mediatek: avoid virtual gpio trying to set reg pinctrl: mediatek: update pinmux definitions for mt6779 pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API pinctrl: mcp23s08: Use irqchip template pinctrl: sx150x: Use irqchip template dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes pinctrl: intel: Add Intel Emmitsburg pin controller support pinctl: ti: iodelay: Replace HTTP links with HTTPS ones Revert "gpio: omap: handle pin config bias flags" pinctrl: single: Use fallthrough pseudo-keyword pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword pinctrl: baytrail: Use fallthrough pseudo-keyword ...

Merge tag 'pinctrl-v5.8-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2020-08-01T17:11:42+00:00

Pull pin control fix from Linus Walleij: "A single last minute pin control fix to the Qualcomm driver fixing missing dual edge PCH interrupts" * tag 'pinctrl-v5.8-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180

pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword

2020-07-20T13:38:27+00:00

Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva Link: https://lore.kernel.org/r/20200716212213.GA17623@embeddedor Signed-off-by: Linus Walleij

pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180

2020-07-16T13:41:41+00:00

Depending on how you look at it, you can either say that: a) There is a PDC hardware issue (with the specific IP rev that exists on sc7180) that causes the PDC not to work properly when configured to handle dual edges. b) The dual edge feature of the PDC hardware was only added in later HW revisions and thus isn't in all hardware. Regardless of how you look at it, let's work around the lack of dual edge support by only ever letting our parent see requests for single edge interrupts on affected hardware. NOTE: it's possible that a driver requesting a dual edge interrupt might get several edges coalesced into a single IRQ. For instance if a line starts low and then goes high and low again, the driver that requested the IRQ is not guaranteed to be called twice. However, it is guaranteed that once the driver's interrupt handler starts running its first instruction that any new edges coming in will cause the interrupt to fire again. This is relatively commonplace for dual-edge gpio interrupts (many gpio controllers require software to emulate dual edge with single edge) so client drivers should be setup to handle it. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Douglas Anderson Reviewed-by: Marc Zyngier Link: https://lore.kernel.org/r/20200714080254.v3.1.Ie0d730120b232a86a4eac1e2909bcbec844d1766@changeid Signed-off-by: Linus Walleij

pinctrl: qcom: pinctrl-msm8976: Remove unused variable 'nav_tsync_groups'

2020-07-16T13:12:38+00:00

Fixes the following W=1 kernel build warning(s): drivers/pinctrl/qcom/pinctrl-msm8976.c:802:27: warning: ‘nav_tsync_groups’ defined but not used [-Wunused-const-variable=] 802 | static const char const nav_tsync_groups[] = { | ^~~~~~~~~~~~~~~~ Signed-off-by: Lee Jones Cc: Andy Gross Cc: Bjorn Andersson Cc: Del Regno Cc: linux-arm-msm@vger.kernel.org Link: https://lore.kernel.org/r/20200713144930.1034632-10-lee.jones@linaro.org Signed-off-by: Linus Walleij