kernel/linux.git/drivers/pinctrl/qcom/Makefile, branch v6.19.11

pinctrl: qcom: sm8350-lpass-lpi: Merge with SC7280 to fix I2S2 and SWR TX pins

2026-01-19T00:13:22+00:00

Qualcomm SC7280 and SM8350 SoCs have slightly different LPASS audio blocks (v9.4.5 and v9.2), however the LPASS LPI pin controllers are exactly the same. The driver for SM8350 has two issues, which can be fixed by simply moving over to SC7280 driver which has them correct: 1. "i2s2_data_groups" listed twice GPIO12, but should have both GPIO12 and GPIO13, 2. "swr_tx_data_groups" contained GPIO5 for "swr_tx_data2" function, but that function is also available on GPIO14, thus listing it twice is not necessary. OTOH, GPIO5 has also "swr_rx_data1", so selecting swr_rx_data function should not block the TX one. Fixes: be9f6d56381d ("pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij

pinctrl: qcom: add the tlmm driver for Kaanapali platforms

2025-10-13T10:26:05+00:00

Add support for Kaanapali TLMM configuration and control via the pinctrl framework. Signed-off-by: Jingyi Wang Reviewed-by: Bartosz Golaszewski Reviewed-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij

pinctrl: qcom: Add SDM660 LPASS LPI TLMM

2025-09-10T13:35:42+00:00

The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring pins related to audio. Add the driver for this. Also, this driver uses predefined pin_offsets for each pin taken from downstream driver, which does not follow the usual 0x1000 distance between pins and uses an array with predefined offsets that do not follow any regular pattern [1]. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Reviewed-by: Konrad Dybcio Signed-off-by: Richard Acayan Co-developed-by: Nickolay Goppen Signed-off-by: Nickolay Goppen Signed-off-by: Linus Walleij

pinctrl: qcom: Add glymur pinctrl driver

2025-09-08T12:56:47+00:00

Add TLMM pinctrl driver to support pin configuration with pinctrl framework for Glymur SoC. Reviewed-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Signed-off-by: Pankaj Patil Signed-off-by: Linus Walleij

pinctrl: qcom: Add Milos pinctrl driver

2025-07-14T15:50:58+00:00

Add pinctrl driver for TLMM block found in the Milos SoC. Signed-off-by: Luca Weiss Reviewed-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/20250702-sm7635-pinctrl-v2-2-c138624b9924@fairphone.com Signed-off-by: Linus Walleij

pinctrl: qcom: Add test case for TLMM interrupt handling

2025-02-28T08:41:14+00:00

While looking at the X1E PDC GPIO interrupts it became clear that we're lacking a convenient and accessible way to validate if the TLMM interrupt code performing as expected. This introduces a kunit-based "hack" that relies on pin bias/pull configuration to tickle the interrupt logic in non-connected pins to allow us to evaluate that an expected number of interrupts are delivered. The bias/pull configuration is done with mmio accesses directly from the test code, to avoid having to programmatically acquire and drive the pinconf interface for the test pin. This limits the scalability of the code to targets with a particular register layout, but serves our needs for now. The pin to be used for testing is specified by the tester using the "tlmm-test.gpio" module parameter. Worth mentioning is that some of the test cases currently fails for GPIOs that is not backed by PDC (i.e. "non-wakeup" GPIOs), as lingering latched interrupt state is being delivered at IRQ request time. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/20250227-tlmm-test-v1-1-d18877b4a5db@oss.qualcomm.com Signed-off-by: Linus Walleij

pinctrl: qcom: Add MSM8917 tlmm pinctrl driver

2024-12-16T14:15:35+00:00

It is based on MSM8916 driver with the pinctrl definitions from Qualcomm's downstream MSM8917 driver. Signed-off-by: Otto Pflüger Reviewed-by: Dmitry Baryshkov Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/20241215-msm8917-v9-3-bacaa26f3eef@mainlining.org Signed-off-by: Linus Walleij

pinctrl: qcom: Add sm8750 pinctrl driver

2024-11-13T13:45:58+00:00

Add TLMM pinctrl driver to support pin configuration with pinctrl framework for sm8750 SoC. Signed-off-by: Melody Olvera Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/20241112002843.2804490-3-quic_molvera@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: add support for TLMM on SAR2130P

2024-10-22T12:43:45+00:00

Add driver for the pincontrol device as present on the Qualcomm SAR2130P platform. This is based on the msm-5.10 tree, tag KERNEL.PLATFORM.1.0.r4-00400-NEO.0. Co-developed-by: Mayank Grover Signed-off-by: Mayank Grover Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/20241018-sar2130p-tlmm-v2-2-11a1d09a6e5f@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: add the tlmm driver for QCS8300 platforms

2024-10-22T12:41:44+00:00

Add support for QCS8300 TLMM configuration and control via the pinctrl framework. Signed-off-by: Jingyi Wang Link: https://lore.kernel.org/20241018-qcs8300_tlmm-v3-2-8b8d3957cf1a@quicinc.com Signed-off-by: Linus Walleij